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�� � 8 � ( t " amd,seattle-overdrive amd,seattle + 8 7Linaro 96Boards Enterprise Edition Server (Husky) Board interrupt-controller@e1101000 arm,gic-400 arm,cortex-a15-gic = R + @ c � �� � � g r � y v2m@e0080000 arm,gic-v2m-frame � c y timer arm,armv8-timer 0 g
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� pmu arm,armv8-pmuv3 ` g
smb simple-bus + r � clk100mhz_0 fixed-clock � ��� �adl3clk_100mhz clk375mhz fixed-clock � �Z � �ccpclk_375mhz clk333mhz fixed-clock � ��-@ �sataclk_333mhz y clk500mhz_0 fixed-clock � � �e �pcieclk_500mhz clk500mhz_1 fixed-clock � � �e �dmaclk_500mhz clk250mhz_4 fixed-clock � �沀 �miscclk_250mhz y clk100mhz_1 fixed-clock � ��� �uartspiclk_100mhz y sata@e0300000 snps,dwc-ahci c �0 g c � � sata@e0d00000 �disabled snps,dwc-ahci c �� g b � � i2c@e1000000 �ok snps,designware-i2c c � g e � i2c@e0050000 �ok snps,designware-i2c c � g T � serial@e1010000 arm,pl011 arm,primecell c � g H � �uartclk apb_pclk spi@e1020000 �ok arm,pl022 arm,primecell c � � g J � �apb_pclk spi@e1030000 �ok arm,pl022 arm,primecell c � � g I � �apb_pclk + sdcard@0
mmc-spi-slot c 1- �
H ) 9 I X l gpio@e1040000 �disabled arm,pl061 arm,primecell � c � � g g = R � �apb_pclk gpio@e1050000 �ok arm,pl061 arm,primecell � c � � = R g f � �apb_pclk gpio@e0020000 �ok arm,pl061 arm,primecell � c � � = R g n � �apb_pclk gpio@e0030000 �ok arm,pl061 arm,primecell � c � � = R g m � �apb_pclk gpio@e0080000 �ok arm,pl061 arm,primecell � c � � = R g i � �apb_pclk ccp@e0100000 �ok amd,ccp-seattle-v1a c � g � � pcie@f0000000 pci-host-ecam-generic + R �pci � � c � � � � � ! " # � �C T r � @ @ � �ok ccn@e8000000 arm,ccn-504 c � g | kcs@e0010000 �disabled ipmi-kcs �ipmi c � g � � � clk250mhz_0 fixed-clock � �沀 �xgmacclk0_dma_250mhz y clk250mhz_1 fixed-clock � �沀 �xgmacclk0_ptp_250mhz y clk250mhz_2 fixed-clock � �沀 �xgmacclk1_dma_250mhz y clk250mhz_3 fixed-clock � �沀 �xgmacclk1_ptp_250mhz y xgmac@e0700000 amd,xgbe-seattle-v1a P c �p �x �$ �% ` �% � H g E Z [ \ ] C , < P
c u � ������ � �dma_clk ptp_clk �xgmii � � y
xgmac@e0900000 amd,xgbe-seattle-v1a P c � � �$ �% � ` �% � H g D U V W X B , < P
c u � ������ � �dma_clk ptp_clk �xgmii � � y smmu@e0600000 arm,mmu-401 c �` � g P P D �
smmu@e0800000 arm,mmu-401 c � � g O O D � chosen �/smb/serial@e1010000 psci
arm,psci-0.2 �smc compatible interrupt-parent #address-cells #size-cells model interrupt-controller #interrupt-cells reg interrupts ranges phandle msi-controller dma-ranges #clock-cells clock-frequency clock-output-names clocks dma-coherent status clock-names spi-controller num-cs spi-max-frequency voltage-ranges pl022,hierarchy pl022,interface pl022,com-mode pl022,rx-level-trig pl022,tx-level-trig #gpio-cells gpio-controller amd,zlib-support device_type bus-range msi-parent interrupt-map-mask interrupt-map reg-size reg-spacing amd,per-channel-interrupt amd,speed-set amd,serdes-blwc amd,serdes-cdr-rate amd,serdes-pq-skew amd,serdes-tx-amp amd,serdes-dfe-tap-config amd,serdes-dfe-tap-enable mac-address phy-mode #stream-id-cells #global-interrupts mmu-masters stdout-path method