�
�� ?/ 8 < ( / ;� apm,merlin apm,xgene-shadowcat + 7APM X-Gene Merlin board cpus + cpu@0 =cpu apm,strega I Mspin-table [ �� l } � cpu@1 =cpu apm,strega I Mspin-table [ �� l } � cpu@100 =cpu apm,strega I Mspin-table [ �� l } � cpu@101 =cpu apm,strega I Mspin-table [ �� l } � cpu@200 =cpu apm,strega I Mspin-table [ �� l } � cpu@201 =cpu apm,strega I Mspin-table [ �� l } � cpu@300 =cpu apm,strega I Mspin-table [ �� l } � cpu@301 =cpu apm,strega I Mspin-table [ �� l } � l2-cache-0 cache � l2-cache-1 cache � l2-cache-2 cache � l2-cache-3 cache � interrupt-controller@78090000 arm,cortex-a15-gic � + � � � y � @ I x x
x x � v2m@0 arm,gic-v2m-frame � I � v2m@10000 arm,gic-v2m-frame � I v2m@20000 arm,gic-v2m-frame � I v2m@30000 arm,gic-v2m-frame � I v2m@40000 arm,gic-v2m-frame � I v2m@50000 arm,gic-v2m-frame � I v2m@60000 arm,gic-v2m-frame � I v2m@70000 arm,gic-v2m-frame � I v2m@80000 arm,gic-v2m-frame � I v2m@90000 arm,gic-v2m-frame � I v2m@a0000 arm,gic-v2m-frame � I
v2m@b0000 arm,gic-v2m-frame � I v2m@c0000 arm,gic-v2m-frame � I v2m@d0000 arm,gic-v2m-frame � I
v2m@e0000 arm,gic-v2m-frame � I v2m@f0000 arm,gic-v2m-frame � I pmu arm,armv8-pmuv3 � � timer arm,armv8-timer 0 � �
� � � ��� soc simple-bus + � clocks + � refclk fixed-clock } ��� �refclk �
pmdpll@170000f0 apm,xgene-pcppll-v2-clock } �
I � �pmdpll � pmd0clk@7e200200 apm,xgene-pmd-clock } � I ~ �pmd0clk � pmd1clk@7e200210 apm,xgene-pmd-clock } � I ~ �pmd1clk � pmd2clk@7e200220 apm,xgene-pmd-clock } � I ~ �pmd2clk � pmd3clk@7e200230 apm,xgene-pmd-clock } � I ~ 0 �pmd3clk � socpll@17000120 apm,xgene-socpll-v2-clock } �
I �socpll � socplldiv2 fixed-factor-clock } � �socplldiv2 �
ahbclk@17000000 apm,xgene-device-clock } �
I div-reg " d 1 ? �ahbclk � sbapbclk@1704c000 apm,xgene-device-clock } � I � div-reg " 1 ? �sbapbclk � sdioclk@1f2ac000 apm,xgene-device-clock } �
I *� csr-reg div-reg M X a o " x 1 ? �sdioclk � pcie0clk@1f2bc000 apm,xgene-device-clock } �
I +� csr-reg �pcie0clk � pcie1clk@1f2cc000 apm,xgene-device-clock } �
I ,� csr-reg �pcie1clk � xge0clk@1f61c000 apm,xgene-device-clock } �
I a� csr-reg o X �xge0clk � xge1clk@1f62c000 apm,xgene-device-clock } �
I b� csr-reg o X �xge1clk � rngpkaclk@17000000 apm,xgene-device-clock } �
I csr-reg M X a o
�rngpkaclk � i2c4clk@1704c000 apm,xgene-device-clock } � I � csr-reg M X @ a o @ �i2c4clk � system-clk-controller@17000000 apm,xgene-scu syscon I � reboot@17000014 syscon-reboot { * \ csw@7e200000 apm,xgene-csw syscon I ~ � mcba@7e700000 apm,xgene-mcb syscon I ~p � mcbb@7e720000 apm,xgene-mcb syscon I ~r � efuse@1054a000 apm,xgene-efuse syscon I T� � edac@78800000 apm,xgene-edac + � � � � � I x� $ � ! ' edacmc@7e800000 apm,xgene-edac-mc I ~� � edacmc@7e840000 apm,xgene-edac-mc I ~� � edacmc@7e880000 apm,xgene-edac-mc I ~� � edacmc@7e8c0000 apm,xgene-edac-mc I ~� � edacpmd@7c000000 apm,xgene-edac-pmd I | � edacpmd@7c200000 apm,xgene-edac-pmd I | � edacpmd@7c400000 apm,xgene-edac-pmd I |@ � edacpmd@7c600000 apm,xgene-edac-pmd I |` � edacl3@7e600000 apm,xgene-edac-l3-v2 I ~` edacsoc@7e930000 apm,xgene-edac-soc I ~� pmu@78810000 apm,xgene-pmu-v2 + � � � � I x� � " pmul3c@7e610000 apm,xgene-pmu-l3c I ~a pmuiob@7e940000 apm,xgene-pmu-iob I ~� pmucmcb@7e710000 apm,xgene-pmu-mcb I ~q � pmucmcb@7e730000 apm,xgene-pmu-mcb I ~s � pmucmc@7e810000 apm,xgene-pmu-mc I ~� � pmucmc@7e850000 apm,xgene-pmu-mc I ~� � pmucmc@7e890000 apm,xgene-pmu-mc I ~� � pmucmc@7e8d0000 apm,xgene-pmu-mc I ~� � mailbox@10540000 apm,xgene-slimpro-mbox I T � � ` � � i2cslimpro apm,xgene-slimpro-i2c � hwmonslimpro apm,xgene-slimpro-hwmon � serial@10600000 =serial ns16550 I ` � � ��� � L ok dwusb@19000000 disabled
snps,dwc3 I � ] host pcie@1f2b0000 disabled =pci apm,xgene-pcie apm,xgene2-pcie � + I + �� csr cfg T � � � C � � 8 B � � � B � ( � 2 � E � S pcie@1f2c0000 disabled =pci apm,xgene-pcie apm,xgene2-pcie � + I , �� csr cfg T � � � C � � 8 B � � � B � ( � 2 � E � S sata@1a000000 apm,xgene-ahci-v2 @ I � � � Z ok sata@1a200000 apm,xgene-ahci-v2 @ I ! !� !� � [ ok sata@1a400000 apm,xgene-ahci-v2 @ I @ " "� "� � \ ok mmc@1c000000 arasan,sdhci-4.9a I � I ^ gclk_xin clk_ahb � ok gpio@1f63c000 apm,xgene-gpio I c� @ s � gpio@1c024000 snps,dw-apb-gpio I @ + gpio-controller@0 snps,dw-apb-gpio-port s � � I gpio@17001000 apm,xgene-gpio-sb I � s ` � ( ) * + , - . / � � � � � � mdio@1f610000 apm,xgene-mdio-xfi + I a � � phy@0 I � ethernet@1f610000 apm,xgene2-sgenet ok 0 I a � ` � � ` a � � s �sgmii � ethernet@1f620000 apm,xgene2-xgenet ok 0 I b ` � " ` � l m n o p q r s � � � � s �xgmii rng@10520000 apm,xgene-rng I R � A � i2c@10511000 + snps,designware-i2c I Q � E } � i2c@10640000 + snps,designware-i2c I d � : � rtc@68 dallas,ds1337 I h ok chosen memory =memory I � gpio-keys
gpio-keys button@1
POWER t � poweroff_mbox@10548000 syscon I T� 0 � poweroff@10548010 syscon-poweroff { * \ compatible interrupt-parent #address-cells #size-cells model device_type reg enable-method cpu-release-addr next-level-cache #clock-cells clocks phandle #interrupt-cells interrupt-controller interrupts ranges msi-controller clock-frequency clock-output-names clock-mult clock-div reg-names divider-offset divider-width divider-shift csr-offset csr-mask enable-offset enable-mask regmap regmap-csw regmap-mcba regmap-mcbb regmap-efuse memory-controller pmd-controller enable-bit-index #mbox-cells mboxes reg-shift status dma-coherent dr_mode dma-ranges bus-range interrupt-map-mask interrupt-map msi-parent no-1-8-v clock-names gpio-controller #gpio-cells snps,nr-gpios apm,nr-gpios apm,nr-irqs apm,irq-start local-mac-address phy-connection-type phy-handle channel port-id bus_num label linux,code linux,input-type