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arm,psci-0.2 =smc cpus + cpu@0 Dcpu cavium,thunder P Tpsci cpu@1 Dcpu cavium,thunder P Tpsci cpu@2 Dcpu cavium,thunder P Tpsci cpu@3 Dcpu cavium,thunder P Tpsci cpu@4 Dcpu cavium,thunder P Tpsci cpu@5 Dcpu cavium,thunder P Tpsci cpu@6 Dcpu cavium,thunder P Tpsci cpu@7 Dcpu cavium,thunder P Tpsci cpu@8 Dcpu cavium,thunder P Tpsci cpu@9 Dcpu cavium,thunder P Tpsci cpu@a Dcpu cavium,thunder P
Tpsci cpu@b Dcpu cavium,thunder P Tpsci cpu@c Dcpu cavium,thunder P Tpsci cpu@d Dcpu cavium,thunder P
Tpsci cpu@e Dcpu cavium,thunder P Tpsci cpu@f Dcpu cavium,thunder P Tpsci cpu@100 Dcpu cavium,thunder P Tpsci cpu@101 Dcpu cavium,thunder P Tpsci cpu@102 Dcpu cavium,thunder P Tpsci cpu@103 Dcpu cavium,thunder P Tpsci cpu@104 Dcpu cavium,thunder P Tpsci cpu@105 Dcpu cavium,thunder P Tpsci cpu@106 Dcpu cavium,thunder P Tpsci cpu@107 Dcpu cavium,thunder P Tpsci cpu@108 Dcpu cavium,thunder P Tpsci cpu@109 Dcpu cavium,thunder P Tpsci cpu@10a Dcpu cavium,thunder P
Tpsci cpu@10b Dcpu cavium,thunder P Tpsci cpu@10c Dcpu cavium,thunder P Tpsci cpu@10d Dcpu cavium,thunder P
Tpsci cpu@10e Dcpu cavium,thunder P Tpsci cpu@10f Dcpu cavium,thunder P Tpsci cpu@200 Dcpu cavium,thunder P Tpsci cpu@201 Dcpu cavium,thunder P Tpsci cpu@202 Dcpu cavium,thunder P Tpsci cpu@203 Dcpu cavium,thunder P Tpsci cpu@204 Dcpu cavium,thunder P Tpsci cpu@205 Dcpu cavium,thunder P Tpsci cpu@206 Dcpu cavium,thunder P Tpsci cpu@207 Dcpu cavium,thunder P Tpsci cpu@208 Dcpu cavium,thunder P Tpsci cpu@209 Dcpu cavium,thunder P Tpsci cpu@20a Dcpu cavium,thunder P
Tpsci cpu@20b Dcpu cavium,thunder P Tpsci cpu@20c Dcpu cavium,thunder P Tpsci cpu@20d Dcpu cavium,thunder P
Tpsci cpu@20e Dcpu cavium,thunder P Tpsci cpu@20f Dcpu cavium,thunder P Tpsci timer arm,armv8-timer 0 b
pmu # cavium,thunder-pmu arm,armv8-pmuv3 b soc simple-bus + m refclk50mhz fixed-clock t ��� �refclk50mhz � interrupt-controller@8010,00000000 arm,gic-v3 � + m � P � �� ` b � gic-its@8010,00020000 arm,gic-v3-its � P � serial@87e0,24000000 arm,pl011 arm,primecell P ��$ b � �apb_pclk serial@87e0,25000000 arm,pl011 arm,primecell P ��% b � �apb_pclk aliases �/soc/serial@87e0,24000000 �/soc/serial@87e0,25000000 memory@0 Dmemory P � compatible interrupt-parent #address-cells #size-cells model method device_type reg enable-method interrupts ranges #clock-cells clock-frequency clock-output-names phandle #interrupt-cells interrupt-controller msi-controller clocks clock-names serial0 serial1