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�� ?U 8 <` ( � <( hisilicon,hip06-d03 + & 7Hisilicon Hip06 D03 Development Board psci
arm,psci-0.2 =smc cpus + cpu-map cluster0 core0 D core1 D core2 D core3 D cluster1 core0 D core1 D core2 D core3 D cluster2 core0 D
core1 D core2 D core3 D
cluster3 core0 D core1 D core2 D core3 D cpu@10000 Hcpu arm,cortex-a57 T Xpsci f w cpu@10001 Hcpu arm,cortex-a57 T Xpsci f w cpu@10002 Hcpu arm,cortex-a57 T Xpsci f w cpu@10003 Hcpu arm,cortex-a57 T Xpsci f w cpu@10100 Hcpu arm,cortex-a57 T Xpsci f w cpu@10101 Hcpu arm,cortex-a57 T Xpsci f w cpu@10102 Hcpu arm,cortex-a57 T Xpsci f w cpu@10103 Hcpu arm,cortex-a57 T Xpsci f w cpu@10200 Hcpu arm,cortex-a57 T Xpsci f w
cpu@10201 Hcpu arm,cortex-a57 T Xpsci f w cpu@10202 Hcpu arm,cortex-a57 T Xpsci f w cpu@10203 Hcpu arm,cortex-a57 T Xpsci f w
cpu@10300 Hcpu arm,cortex-a57 T Xpsci f w cpu@10301 Hcpu arm,cortex-a57 T Xpsci f w cpu@10302 Hcpu arm,cortex-a57 T Xpsci f w cpu@10303 Hcpu arm,cortex-a57 T Xpsci f w l2-cache0 cache w l2-cache1 cache w l2-cache2 cache w l2-cache3 cache w interrupt-controller@4d000000 arm,gic-v3 + � � � � P T M M 0 � � � � w msi-controller@c6000000 arm,gic-v3-its � � T � w timer arm,armv8-timer 0 �
pmu arm,cortex-a57-pmu � mbigen_pcie@a0080000 hisilicon,mbigen-v2 T � intc_usb � � � w intc_sas1 � � � w " intc_sas2 � @ � � w # intc_pcie0 � � �
w $ mbigen_dsa@c0080000 hisilicon,mbigen-v2 T � intc_dsaf0 � � � w intc-sas0 � � � w iommu@a0040000 arm,smmu-v3 T � + Idisabled soc simple-bus + � isa@a01b0000 hisilicon,hip06-lpc + T � bt@e4 ipmi-bt Hipmi T � Iokay serial@2f8 ns16550a P T � Iokay refclk fixed-clock P�� ` w usb@a7030000
generic-ohci T � � � Iokay usb@a7020000
generic-ehci T � � � Iokay sub_ctrl_c@60000000 hisilicon,peri-subctrl syscon T ` w dsa_subctrl@c0000000 hisilicon,dsa-subctrl syscon T � w pcie_subctl@a0000000 " hisilicon,pcie-sas-subctrl syscon T � w ! sds_ctrl@c2200000 syscon T � w mdio@603c0000 hisilicon,hns-mdio T `< m 8
8 S Z + ethernet-phy@0 ethernet-phy-ieee802.3-c22 T w ethernet-phy@1 ethernet-phy-ieee802.3-c22 T w dsa@c7000000 + hisilicon,hns-dsaf-v2 {6port-16rss T � � � ` �ppe-base dsaf-base � � � � @ A B C D E F G H I J K L M N O P Q R S T U V W X � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � �
! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~ � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � �
! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? � � w port@0 T � � � �fiber port@1 T � � � �fiber port@4 T � � � � �copper port@5 T � � � � �copper ethernet-4 hisilicon,hns-nic-v2
Iokay ethernet-5 hisilicon,hns-nic-v2
Iokay ethernet-0 hisilicon,hns-nic-v2
Iokay ethernet-1 hisilicon,hns-nic-v2
Iokay sas@c3000000 hisilicon,hip06-sas-v2 T � .P� 7 L
` [ Z0 n 8 � � � � @ A B C D E F G H I K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~ � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x Idisabled sas@a2000000 hisilicon,hip06-sas-v2 T � .P� 7 ! � L
[ Z n � � � " � @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~ � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ Iokay sas@a3000000 hisilicon,hip06-sas-v2 T � .P� 7 ! L
� [ Zp n � � � � # � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � �
` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~ Idisabled pcie@a0090000 hisilicon,hip06-pcie-ecam T � � � � � �� + Hpci 8 � � � � �� � � p � $ � $ � $ � $ � Idisabled memory@0 Hmemory T @ chosen compatible interrupt-parent #address-cells #size-cells model method cpu device_type reg enable-method next-level-cache phandle #interrupt-cells ranges interrupt-controller #redistributor-regions redistributor-stride interrupts msi-controller #msi-cells msi-parent num-pins #iommu-cells dma-coherent hisilicon,broken-prefetch-cmd status clock-frequency #clock-cells subctrl-vbase mode reg-names subctrl-syscon reset-field-offset desc-num buf-size serdes-syscon port-rst-offset port-mode-offset media-type phy-handle ae-handle port-idx-in-ae local-mac-address sas-addr hisilicon,sas-syscon ctrl-reset-reg ctrl-reset-sts-reg ctrl-clock-ena-reg clocks queue-count phy-count hip06-sas-v2-quirk-amt bus-range msi-map msi-map-mask interrupt-map-mask interrupt-map