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�� � 8 �� ( m �l hisilicon,hip07-d05 + & 7Hisilicon Hip07 D05 Development Board psci
arm,psci-0.2 =smc cpus + cpu-map cluster0 core0 D core1 D core2 D core3 D cluster1 core0 D core1 D core2 D core3 D cluster2 core0 D
core1 D core2 D core3 D
cluster3 core0 D core1 D core2 D core3 D cluster4 core0 D core1 D core2 D core3 D cluster5 core0 D core1 D core2 D core3 D cluster6 core0 D core1 D core2 D core3 D cluster7 core0 D core1 D core2 D core3 D ! cluster8 core0 D " core1 D # core2 D $ core3 D % cluster9 core0 D & core1 D ' core2 D ( core3 D ) cluster10 core0 D * core1 D + core2 D , core3 D - cluster11 core0 D . core1 D / core2 D 0 core3 D 1 cluster12 core0 D 2 core1 D 3 core2 D 4 core3 D 5 cluster13 core0 D 6 core1 D 7 core2 D 8 core3 D 9 cluster14 core0 D : core1 D ; core2 D < core3 D = cluster15 core0 D > core1 D ? core2 D @ core3 D A cpu@10000 Hcpu arm,cortex-a72 T Xpsci f B w � cpu@10001 Hcpu arm,cortex-a72 T Xpsci f B w � cpu@10002 Hcpu arm,cortex-a72 T Xpsci f B w � cpu@10003 Hcpu arm,cortex-a72 T Xpsci f B w � cpu@10100 Hcpu arm,cortex-a72 T Xpsci f C w � cpu@10101 Hcpu arm,cortex-a72 T Xpsci f C w � cpu@10102 Hcpu arm,cortex-a72 T Xpsci f C w � cpu@10103 Hcpu arm,cortex-a72 T Xpsci f C w � cpu@10200 Hcpu arm,cortex-a72 T Xpsci f D w �
cpu@10201 Hcpu arm,cortex-a72 T Xpsci f D w � cpu@10202 Hcpu arm,cortex-a72 T Xpsci f D w � cpu@10203 Hcpu arm,cortex-a72 T Xpsci f D w �
cpu@10300 Hcpu arm,cortex-a72 T Xpsci f E w � cpu@10301 Hcpu arm,cortex-a72 T Xpsci f E w � cpu@10302 Hcpu arm,cortex-a72 T Xpsci f E w � cpu@10303 Hcpu arm,cortex-a72 T Xpsci f E w � cpu@30000 Hcpu arm,cortex-a72 T Xpsci f F w � cpu@30001 Hcpu arm,cortex-a72 T Xpsci f F w � cpu@30002 Hcpu arm,cortex-a72 T Xpsci f F w � cpu@30003 Hcpu arm,cortex-a72 T Xpsci f F w � cpu@30100 Hcpu arm,cortex-a72 T Xpsci f G w � cpu@30101 Hcpu arm,cortex-a72 T Xpsci f G w � cpu@30102 Hcpu arm,cortex-a72 T Xpsci f G w � cpu@30103 Hcpu arm,cortex-a72 T Xpsci f G w � cpu@30200 Hcpu arm,cortex-a72 T Xpsci f H w � cpu@30201 Hcpu arm,cortex-a72 T Xpsci f H w � cpu@30202 Hcpu arm,cortex-a72 T Xpsci f H w � cpu@30203 Hcpu arm,cortex-a72 T Xpsci f H w � cpu@30300 Hcpu arm,cortex-a72 T Xpsci f I w � cpu@30301 Hcpu arm,cortex-a72 T Xpsci f I w � cpu@30302 Hcpu arm,cortex-a72 T Xpsci f I w � cpu@30303 Hcpu arm,cortex-a72 T Xpsci f I w � ! cpu@50000 Hcpu arm,cortex-a72 T Xpsci f J w � " cpu@50001 Hcpu arm,cortex-a72 T Xpsci f J w � # cpu@50002 Hcpu arm,cortex-a72 T Xpsci f J w � $ cpu@50003 Hcpu arm,cortex-a72 T Xpsci f J w � % cpu@50100 Hcpu arm,cortex-a72 T Xpsci f K w � & cpu@50101 Hcpu arm,cortex-a72 T Xpsci f K w � ' cpu@50102 Hcpu arm,cortex-a72 T Xpsci f K w � ( cpu@50103 Hcpu arm,cortex-a72 T Xpsci f K w � ) cpu@50200 Hcpu arm,cortex-a72 T Xpsci f L w � * cpu@50201 Hcpu arm,cortex-a72 T Xpsci f L w � + cpu@50202 Hcpu arm,cortex-a72 T Xpsci f L w � , cpu@50203 Hcpu arm,cortex-a72 T Xpsci f L w � - cpu@50300 Hcpu arm,cortex-a72 T Xpsci f M w � . cpu@50301 Hcpu arm,cortex-a72 T Xpsci f M w � / cpu@50302 Hcpu arm,cortex-a72 T Xpsci f M w � 0 cpu@50303 Hcpu arm,cortex-a72 T Xpsci f M w � 1 cpu@70000 Hcpu arm,cortex-a72 T Xpsci f N w � 2 cpu@70001 Hcpu arm,cortex-a72 T Xpsci f N w � 3 cpu@70002 Hcpu arm,cortex-a72 T Xpsci f N w � 4 cpu@70003 Hcpu arm,cortex-a72 T Xpsci f N w � 5 cpu@70100 Hcpu arm,cortex-a72 T Xpsci f O w � 6 cpu@70101 Hcpu arm,cortex-a72 T Xpsci f O w � 7 cpu@70102 Hcpu arm,cortex-a72 T Xpsci f O w � 8 cpu@70103 Hcpu arm,cortex-a72 T Xpsci f O w � 9 cpu@70200 Hcpu arm,cortex-a72 T Xpsci f P w � : cpu@70201 Hcpu arm,cortex-a72 T Xpsci f P w � ; cpu@70202 Hcpu arm,cortex-a72 T Xpsci f P w � < cpu@70203 Hcpu arm,cortex-a72 T Xpsci f P w � = cpu@70300 Hcpu arm,cortex-a72 T Xpsci f Q w � > cpu@70301 Hcpu arm,cortex-a72 T Xpsci f Q w � ? cpu@70302 Hcpu arm,cortex-a72 T Xpsci f Q w � @ cpu@70303 Hcpu arm,cortex-a72 T Xpsci f Q w � A l2-cache0 cache � B l2-cache1 cache � C l2-cache2 cache � D l2-cache3 cache � E l2-cache4 cache � F l2-cache5 cache � G l2-cache6 cache � H l2-cache7 cache � I l2-cache8 cache � J l2-cache9 cache � K l2-cache10 cache � L l2-cache11 cache � M l2-cache12 cache � N l2-cache13 cache � O l2-cache14 cache � P l2-cache15 cache � Q interrupt-controller@4d000000 arm,gic-v3 � + � � � � � T M M @ m @ M @ m @ � � � � � msi-controller@4c000000 arm,gic-v3-its � � T L msi-controller@6c000000 arm,gic-v3-its � � T l � R msi-controller@c6000000 arm,gic-v3-its � � T � � S msi-controller@8c6000000 arm,gic-v3-its � � T � � T msi-controller@4004c000000 arm,gic-v3-its � � T L msi-controller@4006c000000 arm,gic-v3-its � � T l msi-controller@400c6000000 arm,gic-v3-its � � T � � U msi-controller@408c6000000 arm,gic-v3-its � � T � � V timer arm,armv8-timer 0 �
pmu arm,cortex-a72-pmu � interrupt-controller@60080000 hisilicon,mbigen-v2 T ` uart_intc
R � � � � [ interrupt-controller@a0080000 hisilicon,mbigen-v2 T � intc_pcie2_a
S � � �
� n intc_sas1
S � � � � l intc_sas2
S @ � � � � m intc_smmu_pcie
S � � intc_usb
S � � � � \ interrupt-controller@d0080000 hisilicon,mbigen-v2 T � intc_sec
S � � ! � o intc_smmu_alg
S � � � W interrupt-controller@8,d0080000 hisilicon,mbigen-v2 T � intc_sec
T $ � � ! � q intc_smmu_alg
T + � � � X interrupt-controller@400,d0080000 hisilicon,mbigen-v2 T � intc_sec
U D � � ! � s intc_smmu_alg
U K � � � Y interrupt-controller@408,d0080000 hisilicon,mbigen-v2 T � intc_sec
V d � � ! � u intc_smmu_alg
V k � � � Z interrupt-controller@c0080000 hisilicon,mbigen-v2 T � intc_dsaf0
S � � � � ^ intc-roce
S � � " � i intc-sas0
S � � � � j intc_smmu_dsa
S � � iommu@a0040000 arm,smmu-v3 T � + 8 Vdisabled iommu@d0040000 arm,smmu-v3 T � W � � � � ]eventq gerror priq + 8 � p iommu@8d0040000 arm,smmu-v3 T � X � � � � ]eventq gerror priq + 8 � r iommu@400d0040000 arm,smmu-v3 T � Y � � � � ]eventq gerror priq + 8 � t iommu@408d0040000 arm,smmu-v3 T � Z � � � � ]eventq gerror priq + 8 � v soc simple-bus + � isa@a01b0000 hisilicon,hip07-lpc + T � bt@e4 ipmi-bt Hipmi T � Vokay uart@602b0000 arm,sbsa-uart T `+ [ � ' m � { Vokay usb@a7030000
generic-ohci T � \ � � + Vokay usb@a7020000
generic-ehci T � \ � � + Vokay sub_ctrl_c@60000000 hisilicon,peri-subctrl syscon T ` � ] dsa_subctrl@c0000000 hisilicon,dsa-subctrl syscon T � � _ dsa_cpld@78000010 syscon T x { � a pcie_subctl@a0000000 " hisilicon,pcie-sas-subctrl syscon T � � k sds_ctrl@c2200000 syscon T � � ` mdio@603c0000 hisilicon,hns-mdio T `< � ] 8
8 S Z + ethernet-phy@0 ethernet-phy-ieee802.3-c22 T � b ethernet-phy@1 ethernet-phy-ieee802.3-c22 T � c dsa@c7000000 + hisilicon,hns-dsaf-v2 �6port-16rss T � � � ` �ppe-base dsaf-base ^ � _ � � � @ A B C D E F G H I J K L M N O P Q R S T U V W X � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � �
! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~ � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � �
! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? � � + � d port@0 T � ` � a � �� fiber port@1 T � ` � a � �� fiber port@4 T + b � ` � �� copper port@5 T + c � ` � �� copper ethernet@4 hisilicon,hns-nic-v2 6 d @ O Vokay + � g ethernet@5 hisilicon,hns-nic-v2 6 d @ O Vokay + � h ethernet@0 hisilicon,hns-nic-v2 6 d @ O Vokay + � e ethernet@1 hisilicon,hns-nic-v2 6 d @ O Vokay + � f infiniband@c4000000 hisilicon,hns-roce-v1 T � + a e f g h l d x �� + i � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � 5 ]hns-roce-comp-0 hns-roce-comp-1 hns-roce-comp-2 hns-roce-comp-3 hns-roce-comp-4 hns-roce-comp-5 hns-roce-comp-6 hns-roce-comp-7 hns-roce-comp-8 hns-roce-comp-9 hns-roce-comp-10 hns-roce-comp-11 hns-roce-comp-12 hns-roce-comp-13 hns-roce-comp-14 hns-roce-comp-15 hns-roce-comp-16 hns-roce-comp-17 hns-roce-comp-18 hns-roce-comp-19 hns-roce-comp-20 hns-roce-comp-21 hns-roce-comp-22 hns-roce-comp-23 hns-roce-comp-24 hns-roce-comp-25 hns-roce-comp-26 hns-roce-comp-27 hns-roce-comp-28 hns-roce-comp-29 hns-roce-comp-30 hns-roce-comp-31 hns-roce-async hns-roce-common sas@c3000000 hisilicon,hip07-sas-v2 T � �P� � _ �
` � Z0 � 8 � � + j � @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~ � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x Vdisabled sas@a2000000 hisilicon,hip07-sas-v2 T � �P� � k � �
� Z � � � + l � @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~ � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ Vokay sas@a3000000 hisilicon,hip07-sas-v2 T � �P� � k �
� � Zp � � � � + m � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � �
` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~ Vdisabled pcie@a00a0000 hisilicon,hip07-pcie-ecam T �� � �
� � � S � �� + Hpci + 8 � � � � � ! � p 4 n � n � n � n � Vokay crypto@d2000000 hisilicon,hip07-sec T � � � � � � � � � � � �
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� � � o B p + � @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` crypto@8,d2000000 hisilicon,hip07-sec T � � � � � � � � � � � �
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� � � q B r + � @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` crypto@400,d2000000 hisilicon,hip07-sec T � � � � � � � � � � � �
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� � � s B t + � @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` crypto@408,d2000000 hisilicon,hip07-sec T � � � � � � � � � � � �
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� � � u B v + � @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` memory@0 Hmemory T @ w distance-map numa-distance-map-v1 � I
aliases Y/soc/uart@602b0000 chosen aserial0:115200n8 compatible interrupt-parent #address-cells #size-cells model method cpu device_type reg enable-method next-level-cache numa-node-id phandle #interrupt-cells ranges interrupt-controller #redistributor-regions redistributor-stride interrupts msi-controller #msi-cells msi-parent num-pins #iommu-cells dma-coherent hisilicon,broken-prefetch-cmd status interrupt-names current-speed reg-io-width subctrl-vbase mode reg-names subctrl-syscon reset-field-offset desc-num buf-size serdes-syscon cpld-syscon port-rst-offset port-mode-offset mc-mac-mask media-type phy-handle ae-handle port-idx-in-ae local-mac-address eth-handle dsaf-handle node-guid sas-addr hisilicon,sas-syscon ctrl-reset-reg ctrl-reset-sts-reg ctrl-clock-ena-reg queue-count phy-count hip06-sas-v2-quirk-amt bus-range msi-map msi-map-mask interrupt-map-mask interrupt-map iommus distance-matrix serial0 stdout-path