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�� ]� 8 X ( � W� ARM Juno development board (r0) arm,juno arm,vexpress " 1 refclk7372800hz fixed-clock = J p�
Zjuno:uartclk m : clk48mhz fixed-clock = J�l Zclk48mhz m > clk50mhz fixed-clock = J�� Zsmc_clk m refclk100mhz fixed-clock = J�� Zapb_pclk m
refclk400mhz fixed-clock = Jׄ Zfaxi_clk m 4 clk24mhz fixed-clock = Jn6 Zjuno_mb:clk24mhz m clk25mhz fixed-clock = J}x@ Zjuno_mb:clk25mhz m refclk1mhz fixed-clock = J B@ Zjuno_mb:refclk1mhz m refclk32khz fixed-clock = J � Zjuno_mb:refclk32khz m mcc-sb-3v3 regulator-fixed uMCC_SB_3V3 � 2Z� � 2Z� � m gpio-keys
gpio-keys power-button � 2 � � t �POWER � home-button � 2 � � f �HOME � rlock-button � 2 � � � �RLOCK � vol-up-button � 2 � � s �VOL+ � vol-down-button � 2 � � r �VOL- � nmi-button � 2 � � c �NMI � bus@8000000 simple-bus " 1 � � * D E F � � � � � � �
� � � motherboard-bus@8000000 arm,vexpress,v2p-p1 simple-bus " 1 x � 8 R @ flash@0 arm,vexpress-flash cfi-flash R V adisabled partitions arm,arm-firmware-suite ethernet@200000000 smsc,lan9118 smsc,lan9115 R h smii | � � � � � iofpga-bus@300000000 simple-bus " 1 � sysctl@20000 arm,sp810 arm,primecell R � �refclk timclk apb_pclk = 0 Ztimerclken0 timerclken1 timerclken2 timerclken3 � � m apbregs@10000 syscon simple-mfd R led0 register-bit-led % �vexpress:0
heartbeat &on led1 register-bit-led % �vexpress:1 mmc0 &off led2 register-bit-led % �vexpress:2 cpu0 &off led3 register-bit-led % �vexpress:3 cpu1 &off led4 register-bit-led % �vexpress:4 cpu2 &off led5 register-bit-led % �vexpress:5 cpu3 &off led6 register-bit-led % @ �vexpress:6 &off led7 register-bit-led % � �vexpress:7 &off mmc@50000 arm,pl180 arm,primecell R h 4 � B � �mclk apb_pclk kmi@60000 arm,pl050 arm,primecell R h � �KMIREFCLK apb_pclk kmi@70000 arm,pl050 arm,primecell R h � �KMIREFCLK apb_pclk watchdog@f0000 arm,sp805 arm,primecell R h � �wdog_clk apb_pclk timer@110000 arm,sp804 arm,primecell R h � �timclken1 timclken2 apb_pclk timer@120000 arm,sp804 arm,primecell R h � �timclken1 timclken2 apb_pclk rtc@170000 arm,pl031 arm,primecell R h � �apb_pclk gpio@1d0000 arm,pl061 arm,primecell R h � �apb_pclk N ^ j m timer@2a810000 arm,armv7-timer-mem R *� J�� " 1 � *� adisabled frame@2a830000 h < R mhu@2b1f0000 arm,mhu arm,primecell R + $ h $ # % � �
�apb_pclk m 0 iommu@2b400000 arm,mmu-400 arm,smmu-v1 R +@ h & & � � � � adisabled iommu@2b500000 arm,mmu-401 arm,smmu-v1 R +P h ( ( � � � adisabled m / iommu@2b600000 arm,mmu-401 arm,smmu-v1 R +` h * * � � � � m interrupt-controller@2c010000 arm,gic-400 arm,cortex-a15-gic @ R , ,� ,� ,� " 1 j h ? � , m v2m@0 arm,gic-v2m-frame � R m . v2m@10000 arm,gic-v2m-frame � R v2m@20000 arm,gic-v2m-frame � R v2m@30000 arm,gic-v2m-frame � R timer arm,armv8-timer 0 h
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? etf@20010000 arm,coresight-tmc arm,primecell R � �apb_pclk � in-ports port endpoint � m out-ports port endpoint �
m tpiu@20030000 ! arm,coresight-tpiu arm,primecell R � �apb_pclk � in-ports port endpoint � m funnel@20040000 + arm,coresight-dynamic-funnel arm,primecell R � �apb_pclk � out-ports port endpoint � m in-ports " 1 port@0 R endpoint � m port@1 R endpoint � m " port@2 R endpoint � m etr@20070000 arm,coresight-tmc arm,primecell R � � �apb_pclk � � in-ports port endpoint � m stm@20100000 arm,coresight-stm arm,primecell R ( stm-base stm-stimulus-base � �apb_pclk � out-ports port endpoint � m replicator@20120000 / arm,coresight-dynamic-replicator arm,primecell R � �apb_pclk � out-ports " 1 port@0 R endpoint � m port@1 R endpoint � m in-ports port endpoint � m
cpu-debug@22010000 & arm,coresight-cpu-debug arm,primecell R " � �apb_pclk � etm@22040000 " arm,coresight-etm4x arm,primecell R " � �apb_pclk � out-ports port endpoint � m funnel@220c0000 + arm,coresight-dynamic-funnel arm,primecell R " � �apb_pclk � out-ports port endpoint � m in-ports " 1 port@0 R endpoint � m port@1 R endpoint � m cpu-debug@22110000 & arm,coresight-cpu-debug arm,primecell R " � �apb_pclk � etm@22140000 " arm,coresight-etm4x arm,primecell R " � �apb_pclk � out-ports port endpoint � m cpu-debug@23010000 & arm,coresight-cpu-debug arm,primecell R # � �apb_pclk � etm@23040000 " arm,coresight-etm4x arm,primecell R # � �apb_pclk � out-ports port endpoint � ! m # funnel@230c0000 + arm,coresight-dynamic-funnel arm,primecell R # � �apb_pclk � out-ports port endpoint � " m in-ports " 1 port@0 R endpoint � # m ! port@1 R endpoint � $ m ( port@2 R endpoint � % m * port@3 R endpoint � & m , cpu-debug@23110000 & arm,coresight-cpu-debug arm,primecell R # � �apb_pclk � ' etm@23140000 " arm,coresight-etm4x arm,primecell R # � �apb_pclk � ' out-ports port endpoint � ( m $ cpu-debug@23210000 & arm,coresight-cpu-debug arm,primecell R #! � �apb_pclk � ) etm@23240000 " arm,coresight-etm4x arm,primecell R #$ � �apb_pclk � ) out-ports port endpoint � * m % cpu-debug@23310000 & arm,coresight-cpu-debug arm,primecell R #1 � �apb_pclk � + etm@23340000 " arm,coresight-etm4x arm,primecell R #4 � �apb_pclk � + out-ports port endpoint � , m & gpu@2d000000 arm,juno-mali arm,mali-t624 R - $ h ! " job mmu gpu � - � � adisabled sram@2e000000 arm,juno-sram-ns mmio-sram R . � " 1 � . � scp-sram@0 arm,juno-scp-shmem R scp-sram@200 arm,juno-scp-shmem R m 1 pcie@40000000 < arm,juno-r1-pcie plda,xpressrich3-axi pci-host-ecam-generic *pci R @ 6 � @ " 1 � T � _� � P P B @ @ 8 Q � � � C � * � � � � \ . adisabled g v / scpi arm,scpi � 0 � 1 clocks arm,scpi-clocks clocks-0 arm,scpi-dvfs-clocks = � Zatlclk aplclk gpuclk m - clocks-1 arm,scpi-variable-clocks = � Zpxlclk m 6 power-controller arm,scpi-power-domains � � m sensors arm,scpi-sensors � m 2 thermal-zones pmic � � � d � 2 trips trip0 _� � 1critical soc � � � d � 2 trips trip0 8� � 1critical big-cluster � � � d � 2 adisabled little-cluster � � � d � 2 adisabled gpu0 � � � d � 2 adisabled gpu1 � � � d � 2 adisabled iommu@7fb00000 arm,mmu-401 arm,smmu-v1 R � h _ _ � � � m 3 iommu@7fb10000 arm,mmu-401 arm,smmu-v1 R � h c c � � m 5 iommu@7fb20000 arm,mmu-401 arm,smmu-v1 R � h a a � � m 8 iommu@7fb30000 arm,mmu-401 arm,smmu-v1 R � h e e � � � m = dma@7ff00000 arm,pl330 arm,primecell R � ' 5 l h X Y Z [ \ l m n o H � 3 3 3 3 3 3 3 3 3 � 4 �apb_pclk hdlcd@7ff50000
arm,hdlcd R � h ] � 5 � 6 �pxlclk port endpoint � 7 m < hdlcd@7ff60000
arm,hdlcd R � h U � 8 � 6 �pxlclk port endpoint � 9 m ; serial@7ff80000 arm,pl011 arm,primecell R � h S � :
�uartclk apb_pclk i2c@7ffa0000 snps,designware-i2c R � " 1 h h J � C � � hdmi-transmitter@70 nxp,tda998x R p port endpoint � ; m 9 hdmi-transmitter@71 nxp,tda998x R q port endpoint � < m 7 usb@7ffb0000
generic-ohci R � h t � = � > usb@7ffc0000
generic-ehci R � h u � = � > memory-controller@7ffd0000 arm,pl354 arm,primecell R � h V W � �apb_pclk memory@80000000 *memory R � � � tlx-bus@60000000 simple-bus " 1 � ` * � aliases X/serial@7ff80000 chosen `serial0:115200n8 psci
arm,psci-0.2 lsmc cpus " 1 cpu-map cluster0 core0 core1 cluster1 core0 core1 ' core2 ) core3 + idle-states spsci cpu-sleep-0 arm,idle-state � � � , � � � � m @ cluster-sleep-0 arm,idle-state � � � � � � � � m A cpu@0 arm,cortex-a57 R *cpu �psci � � � @ � ! @ 3 @ ? � - Q @ A a t m cpu@1 arm,cortex-a57 R *cpu �psci � � � @ � ! @ 3 @ ? � - Q @ A a t m cpu@100 arm,cortex-a53 R *cpu �psci � � � @ � ! @ 3 � @ B � - Q @ A a B t � m cpu@101 arm,cortex-a53 R *cpu �psci � � � @ � ! @ 3 � @ B � - Q @ A a B t � m ' cpu@102 arm,cortex-a53 R *cpu �psci � � � @ � ! @ 3 � @ B � - Q @ A a B t � m ) cpu@103 arm,cortex-a53 R *cpu �psci � � � @ � ! @ 3 � @ B � - Q @ A a B t � m + l2-cache0 cache � � @ m ? l2-cache1 cache � � @ m B pmu-a57 arm,cortex-a57-pmu h � pmu-a53 arm,cortex-a53-pmu 0 h � ' ) + model compatible interrupt-parent #address-cells #size-cells #clock-cells clock-frequency clock-output-names phandle regulator-name regulator-min-microvolt regulator-max-microvolt regulator-always-on debounce-interval wakeup-source linux,code label gpios ranges #interrupt-cells interrupt-map-mask interrupt-map arm,hbi arm,vexpress,site reg bank-width status interrupts phy-mode reg-io-width smsc,irq-active-high smsc,irq-push-pull clocks vdd33a-supply vddvario-supply clock-names assigned-clocks assigned-clock-parents offset linux,default-trigger default-state max-frequency vmmc-supply gpio-controller #gpio-cells interrupt-controller frame-number #mbox-cells #iommu-cells #global-interrupts power-domains dma-coherent msi-controller remote-endpoint iommus arm,scatter-gather reg-names cpu interrupt-names device_type bus-range linux,pci-domain dma-ranges msi-parent iommu-map-mask iommu-map mboxes shmem clock-indices num-domains #power-domain-cells #thermal-sensor-cells polling-delay polling-delay-passive thermal-sensors temperature hysteresis #dma-cells #dma-channels #dma-requests i2c-sda-hold-time-ns serial0 stdout-path method entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us enable-method i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache cpu-idle-states capacity-dmips-mhz dynamic-power-coefficient interrupt-affinity