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�� H� 8 E� ( � E� ,Freescale i.MX8QM MEK 2fsl,imx8qm-mek fsl,imx8qm aliases =/bus@5b000000/mmc@5b010000 B/bus@5b000000/mmc@5b020000 G/bus@5b000000/mmc@5b030000 L/bus@5a000000/serial@5a060000 cpus cpu@0 Tcpu 2arm,cortex-a53 arm,armv8 ` dpsci r cpu@1 Tcpu 2arm,cortex-a53 arm,armv8 ` dpsci r cpu@2 Tcpu 2arm,cortex-a53 arm,armv8 ` dpsci r cpu@3 Tcpu 2arm,cortex-a53 arm,armv8 ` dpsci r l2-cache0 2cache � l2-cache1 2cache interrupt-controller@51a00000 2arm,gic-v3 P ` Q� Q� R R R � � � � pmu 2arm,armv8-pmuv3 � psci
2arm,psci-1.0 ksmc timer 2arm,armv8-timer 0 �
scu 2fsl,imx-scu
�tx0 rx0 gip3 $ � imx8qx-pd 2fsl,imx8qm-scu-pd fsl,scu-pd � � clock-controller 2fsl,imx8qm-clk fsl,scu-clk � � pinctrl 2fsl,imx8qm-iomuxc fec1grp � � � � � � � � � � � � � � � � � lpuart0grp � �
usdhc1grp � � � A � ! � ! � ! � ! � ! � ! � ! � ! � ! � A � usdhc2grp T � � A � ! � ! � ! � ! � ! � ! � bus@58000000 2simple-bus �X X clock-img-ipg 2fixed-clock � � �� img_ipg_clk � jpegdec@58400000 `X@ 0 � 5 6 7 8 " )per ipg 5 E �� �� ( Z � � � � % 2nxp,imx8qm-jpgdec nxp,imx8qxp-jpgdec jpegenc@58450000 `XE 0 � 1 2 3 4 " )per ipg 5 E �� �� ( Z � � � � % 2nxp,imx8qm-jpgenc nxp,imx8qxp-jpgenc clock-controller@585d0000 2fsl,imx8qxp-lpcg `X] � " h 0 img_jpeg_dec_lpcg_clk img_jpeg_dec_lpcg_ipg_clk Z � clock-controller@585f0000 2fsl,imx8qxp-lpcg `X_ � " h 0 img_jpeg_enc_lpcg_clk img_jpeg_enc_lpcg_ipg_clk Z � bus@5a000000 2simple-bus �Z Z clock-dma-ipg 2fixed-clock � �' dma_ipg_clk � serial@5a060000 `Z � � " )ipg baud 5 9 EĴ Z 9 vokay % 2fsl,imx8qm-lpuart fsl,imx8qxp-lpuart }default �
serial@5a070000 `Z � � " )ipg baud 5 : EĴ Z : vdisabled % 2fsl,imx8qm-lpuart fsl,imx8qxp-lpuart serial@5a080000 `Z � � " )ipg baud 5 ; EĴ Z ; vdisabled % 2fsl,imx8qm-lpuart fsl,imx8qxp-lpuart serial@5a090000 `Z � � "
)ipg baud 5 < EĴ Z < vdisabled % 2fsl,imx8qm-lpuart fsl,imx8qxp-lpuart clock-controller@5a460000 2fsl,imx8qxp-lpcg `ZF � " 9 h ' uart0_lpcg_baud_clk uart0_lpcg_ipg_clk Z 9 � clock-controller@5a470000 2fsl,imx8qxp-lpcg `ZG � " : h ' uart1_lpcg_baud_clk uart1_lpcg_ipg_clk Z : � clock-controller@5a480000 2fsl,imx8qxp-lpcg `ZH � " ; h ' uart2_lpcg_baud_clk uart2_lpcg_ipg_clk Z ; � clock-controller@5a490000 2fsl,imx8qxp-lpcg `ZI � " < h ' uart3_lpcg_baud_clk uart3_lpcg_ipg_clk Z < �
i2c@5a800000 `Z� @ � � " )per 5 ` En6 Z ` vdisabled # 2fsl,imx8qm-lpi2c fsl,imx7ulp-lpi2c i2c@5a810000 `Z� @ � � " )per 5 a En6 Z a vdisabled # 2fsl,imx8qm-lpi2c fsl,imx7ulp-lpi2c i2c@5a820000 `Z� @ � � " )per 5 b En6 Z b vdisabled # 2fsl,imx8qm-lpi2c fsl,imx7ulp-lpi2c i2c@5a830000 `Z� @ � � " )per 5 c En6 Z c vdisabled # 2fsl,imx8qm-lpi2c fsl,imx7ulp-lpi2c clock-controller@5ac00000 2fsl,imx8qxp-lpcg `Z� � " ` h i2c0_lpcg_clk i2c0_lpcg_ipg_clk Z ` � clock-controller@5ac10000 2fsl,imx8qxp-lpcg `Z� � " a h i2c1_lpcg_clk i2c1_lpcg_ipg_clk Z a � clock-controller@5ac20000 2fsl,imx8qxp-lpcg `Z� � " b h i2c2_lpcg_clk i2c2_lpcg_ipg_clk Z b � clock-controller@5ac30000 2fsl,imx8qxp-lpcg `Z� � " c h i2c3_lpcg_clk i2c3_lpcg_ipg_clk Z c � clock-controller@5a4a0000 2fsl,imx8qxp-lpcg `ZJ � " = h ' uart4_lpcg_baud_clk uart4_lpcg_ipg_clk Z = bus@5b000000 2simple-bus �[ [ clock-conn-axi 2fixed-clock � ��CU
conn_axi_clk � clock-conn-ahb 2fixed-clock � � �!�
conn_ahb_clk clock-conn-ipg 2fixed-clock � ����
conn_ipg_clk � mmc@5b010000 � � `[ " )ipg ahb per Z � vokay 3 2fsl,imx8qm-usdhc fsl,imx8qxp-usdhc fsl,imx7d-usdhc }default � � � � � mmc@5b020000 � � `[ " )ipg ahb per Z � � � vokay 3 2fsl,imx8qm-usdhc fsl,imx8qxp-usdhc fsl,imx7d-usdhc }default � � � � � mmc@5b030000 � � `[ " )ipg ahb per Z � vdisabled ethernet@5b040000 `[ 0 � " )ipg ahb enet_clk_ref ptp 5 � � E沀sY@ � Z � vokay 2fsl,imx8qm-fec fsl,imx6sx-fec }default � "rgmii-id + 6 mdio ethernet-phy@0 2ethernet-phy-ieee802.3-c22 ` � ethernet-phy@1 2ethernet-phy-ieee802.3-c22 ` ethernet@5b050000 `[ 0 � " )ipg ahb enet_clk_ref ptp 5 � � E沀sY@ � Z � vdisabled 2fsl,imx8qm-fec fsl,imx6sx-fec clock-controller@5b200000 2fsl,imx8qxp-lpcg `[ � " � h 9 sdhc0_lpcg_per_clk sdhc0_lpcg_ipg_clk sdhc0_lpcg_ahb_clk Z � � clock-controller@5b210000 2fsl,imx8qxp-lpcg `[! � " � h 9 sdhc1_lpcg_per_clk sdhc1_lpcg_ipg_clk sdhc1_lpcg_ahb_clk Z � � clock-controller@5b220000 2fsl,imx8qxp-lpcg `[" � " � h 9 sdhc2_lpcg_per_clk sdhc2_lpcg_ipg_clk sdhc2_lpcg_ahb_clk Z � � clock-controller@5b230000 2fsl,imx8qxp-lpcg `[# � 0 " � � � h � enet0_lpcg_timer_clk enet0_lpcg_txc_sampling_clk enet0_lpcg_ahb_clk enet0_lpcg_rgmii_txc_clk enet0_lpcg_ipg_clk enet0_lpcg_ipg_s_clk Z � � clock-controller@5b240000 2fsl,imx8qxp-lpcg `[$ � 0 " � � � h � enet1_lpcg_timer_clk enet1_lpcg_txc_sampling_clk enet1_lpcg_ahb_clk enet1_lpcg_rgmii_txc_clk enet1_lpcg_ipg_clk enet1_lpcg_ipg_s_clk Z � � bus@5d000000 2simple-bus �] ] clock-lsio-mem 2fixed-clock � � ��
lsio_mem_clk clock-lsio-bus 2fixed-clock � ���
lsio_bus_clk � gpio@5d080000 `] � � G W � � Z � 2fsl,imx8qm-gpio fsl,imx35-gpio gpio@5d090000 `] � � G W � � Z � 2fsl,imx8qm-gpio fsl,imx35-gpio gpio@5d0a0000 `]
� � G W � � Z � 2fsl,imx8qm-gpio fsl,imx35-gpio gpio@5d0b0000 `] � � G W � � Z � 2fsl,imx8qm-gpio fsl,imx35-gpio gpio@5d0c0000 `] � � G W � � Z � 2fsl,imx8qm-gpio fsl,imx35-gpio � ! gpio@5d0d0000 `]
� � G W � � Z � 2fsl,imx8qm-gpio fsl,imx35-gpio � gpio@5d0e0000 `] � � G W � � Z � 2fsl,imx8qm-gpio fsl,imx35-gpio gpio@5d0f0000 `] � � G W � � Z � 2fsl,imx8qm-gpio fsl,imx35-gpio mailbox@5d1b0000 `] � � c vdisabled , 2fsl,imx8-mu-scu fsl,imx8qm-mu fsl,imx6sx-mu mailbox@5d1c0000 `] � � c , 2fsl,imx8-mu-scu fsl,imx8qm-mu fsl,imx6sx-mu � mailbox@5d1d0000 `] � � c vdisabled , 2fsl,imx8-mu-scu fsl,imx8qm-mu fsl,imx6sx-mu mailbox@5d1e0000 `] � � c vdisabled , 2fsl,imx8-mu-scu fsl,imx8qm-mu fsl,imx6sx-mu mailbox@5d1f0000 `] � � c vdisabled , 2fsl,imx8-mu-scu fsl,imx8qm-mu fsl,imx6sx-mu mailbox@5d280000 `]( � � c Z � 2fsl,imx8qm-mu fsl,imx6sx-mu clock-controller@5d400000 2fsl,imx8qxp-lpcg `]@ � 4 " � � � � h h pwm0_lpcg_ipg_clk pwm0_lpcg_ipg_hf_clk pwm0_lpcg_ipg_s_clk pwm0_lpcg_ipg_slv_clk pwm0_lpcg_ipg_mstr_clk Z � clock-controller@5d410000 2fsl,imx8qxp-lpcg `]A � 4 " � � � � h h pwm1_lpcg_ipg_clk pwm1_lpcg_ipg_hf_clk pwm1_lpcg_ipg_s_clk pwm1_lpcg_ipg_slv_clk pwm1_lpcg_ipg_mstr_clk Z � clock-controller@5d420000 2fsl,imx8qxp-lpcg `]B � 4 " � � � � h h pwm2_lpcg_ipg_clk pwm2_lpcg_ipg_hf_clk pwm2_lpcg_ipg_s_clk pwm2_lpcg_ipg_slv_clk pwm2_lpcg_ipg_mstr_clk Z � clock-controller@5d430000 2fsl,imx8qxp-lpcg `]C � 4 " � � � � h h pwm3_lpcg_ipg_clk pwm3_lpcg_ipg_hf_clk pwm3_lpcg_ipg_s_clk pwm3_lpcg_ipg_slv_clk pwm3_lpcg_ipg_mstr_clk Z � clock-controller@5d440000 2fsl,imx8qxp-lpcg `]D � 4 " � � � � h h pwm4_lpcg_ipg_clk pwm4_lpcg_ipg_hf_clk pwm4_lpcg_ipg_s_clk pwm4_lpcg_ipg_slv_clk pwm4_lpcg_ipg_mstr_clk Z � clock-controller@5d450000 2fsl,imx8qxp-lpcg `]E � 4 " � � � � h h pwm5_lpcg_ipg_clk pwm5_lpcg_ipg_hf_clk pwm5_lpcg_ipg_s_clk pwm5_lpcg_ipg_slv_clk pwm5_lpcg_ipg_mstr_clk Z � clock-controller@5d460000 2fsl,imx8qxp-lpcg `]F � 4 " � � � � h h pwm6_lpcg_ipg_clk pwm6_lpcg_ipg_hf_clk pwm6_lpcg_ipg_s_clk pwm6_lpcg_ipg_slv_clk pwm6_lpcg_ipg_mstr_clk Z � clock-controller@5d470000 2fsl,imx8qxp-lpcg `]G � 4 " � � � � h h pwm7_lpcg_ipg_clk pwm7_lpcg_ipg_hf_clk pwm7_lpcg_ipg_s_clk pwm7_lpcg_ipg_slv_clk pwm7_lpcg_ipg_mstr_clk Z � chosen o/bus@5a000000/serial@5a060000 memory@80000000 Tmemory ` � @ usdhc2-vmmc 2regulator-fixed {SD1_SPWR � -� � -� � ! � � interrupt-parent #address-cells #size-cells model compatible mmc0 mmc1 mmc2 serial0 device_type reg enable-method next-level-cache phandle #interrupt-cells interrupt-controller interrupts mbox-names mboxes #power-domain-cells #clock-cells fsl,pins ranges clock-frequency clock-output-names clocks clock-names assigned-clocks assigned-clock-rates power-domains clock-indices status pinctrl-names pinctrl-0 bus-width no-sd no-sdio non-removable fsl,tuning-start-tap fsl,tuning-step vmmc-supply cd-gpios wp-gpios fsl,num-tx-queues fsl,num-rx-queues phy-mode phy-handle fsl,magic-packet gpio-controller #gpio-cells #mbox-cells stdout-path regulator-name regulator-min-microvolt regulator-max-microvolt gpio enable-active-high