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�� Q� 8 M� ( � M� ) microchip,sparx5-pcb135 microchip,sparx5 + % 7Sparx5 PCB135 Reference Board (NAND) aliases =/axi@600000000/spi@600104000 B/axi@600000000/serial@600100000 J/axi@600000000/serial@600102000 chosen Rserial0:115200n8 cpus + cpu-map cluster0 core0 ^ core1 ^ cpu@0 arm,cortex-a53 bcpu n rspin-table � � cpu@1 arm,cortex-a53 bcpu n rspin-table � � l2-cache0 cache � arm-pmu arm,cortex-a53-pmu � � psci
arm,psci-0.2 ysmc �disabled timer arm,armv8-timer 0 �
lcpll-clk fixed-clock � ˕� � clock-controller@61110000c microchip,sparx5-dpll � � n $ � ahb-clk fixed-clock � �沀 � sys-clk fixed-clock � �%@�@ � axi@600000000 simple-bus + � interrupt-controller@600300000 arm,gic-v3 � + � < n 0 4 ! " � � syscon@600000000 . microchip,sparx5-cpu-syscon syscon simple-mfd n � � mux-controller mmio-mux " � � � reset-controller@611010008 microchip,sparx5-switch-reset n 0gcb : G � serial@600100000 R \default ns16550a n � j w � �okay serial@600102000 R \default ns16550a n � j w �
�okay spi@600104000 + microchip,sparx5-spi n @ @ � j w � �
�okay R
\default spi-flash@0 jedec,spi-nor � z n spi@0 spi-mux � + n spi-flash@9 jedec,spi-nor � z n spi@e spi-mux � + n spi-flash@6 spi-nand R \default n ��ހ � timer@600105000 snps,dw-apb-timer n P � �timer � mmc@600800000 microchip,dw-sparx5-sdhci �disabled n � R
\default � �core � �/� � � pinctrl@6110101e0 microchip,sparx5-pinctrl n � � P� � @ � � � � cs1-pins GPIO_16 "si cs2-pins GPIO_17 "si cs3-pins GPIO_18 "si si2-pins GPIO_39 GPIO_40 GPIO_41 "si2 �
sgpio-pins GPIO_0 GPIO_1 GPIO_2 GPIO_3 "sg0 � sgpio1-pins GPIO_4 GPIO_5 GPIO_12 GPIO_13 "sg1 � sgpio2-pins GPIO_30 GPIO_31 GPIO_32 GPIO_33 "sg2 � uart-pins GPIO_10 GPIO_11 "uart � uart2-pins GPIO_26 GPIO_27 "uart2 � i2c-pins GPIO_14 GPIO_15 "twi � i2c2-pins GPIO_28 GPIO_29 "twi2 � emmc-pins p GPIO_34 GPIO_35 GPIO_36 GPIO_37 GPIO_38 GPIO_39 GPIO_40 GPIO_41 GPIO_42 GPIO_43 GPIO_44 GPIO_45 GPIO_46 GPIO_47 "emmc �
miim1-pins GPIO_56 GPIO_57 "miim � miim2-pins GPIO_58 GPIO_59 "miim � miim3-pins GPIO_52 GPIO_53 "miim � i2cmux-pins-i GPIO_35 GPIO_36 GPIO_50 GPIO_51
"twi_scl_m + � U i2cmux-0 GPIO_35
"twi_scl_m 6 � Q i2cmux-1 GPIO_36
"twi_scl_m 6 � R i2cmux-2 GPIO_50
"twi_scl_m 6 � S i2cmux-3 GPIO_51
"twi_scl_m 6 � T cs14-pins GPIO_44 "si � gpio@61101036c + microchip,sparx5-sgpio �disabled � R \default B Iswitch n l gpio@0 microchip,sparx5-sgpio-bank n � U ` � � � gpio@1 microchip,sparx5-sgpio-bank n � U ` gpio@611010484 + microchip,sparx5-sgpio �okay � R \default B Iswitch n � \ gpio@0 microchip,sparx5-sgpio-bank n � U @ � � � gpio@1 microchip,sparx5-sgpio-bank n � U @ � \ gpio@61101059c + microchip,sparx5-sgpio �okay � R \default B Iswitch n � \ gpio@0 n microchip,sparx5-sgpio-bank � U ` � � � � X gpio@1 microchip,sparx5-sgpio-bank n � U ` � W i2c@600101000 snps,designware-i2c �okay R \default n + � x , � �� � � P i2c@600103000 snps,designware-i2c �disabled R \default n 0 + � x , � �� � tmon@610508110 microchip,sparx5-temp n P� � � mdio@6110102b0 mscc,ocelot-miim �ok + n � $ ethernet-phy@0 n � ethernet-phy@1 n � ethernet-phy@2 n � ethernet-phy@3 n � ethernet-phy@4 n � ethernet-phy@5 n � ethernet-phy@6 n � ! ethernet-phy@7 n � " ethernet-phy@8 n � # ethernet-phy@9 n � $ ethernet-phy@10 n
� % ethernet-phy@11 n � & ethernet-phy@12 n � ' ethernet-phy@13 n
� ( ethernet-phy@14 n � ) ethernet-phy@15 n � * ethernet-phy@16 n � + ethernet-phy@17 n � , ethernet-phy@18 n � - ethernet-phy@19 n � . ethernet-phy@20 n � / ethernet-phy@21 n � 0 ethernet-phy@22 n � 1 ethernet-phy@23 n � 2 mdio@6110102d4 mscc,ocelot-miim �ok R \default + n � $ ethernet-phy@24 n � 3 ethernet-phy@25 n � 4 ethernet-phy@26 n � 5 ethernet-phy@27 n � 6 ethernet-phy@28 n � 7 ethernet-phy@29 n � 8 ethernet-phy@30 n � 9 ethernet-phy@31 n � : ethernet-phy@32 n � ; ethernet-phy@33 n � < ethernet-phy@34 n
� = ethernet-phy@35 n � > ethernet-phy@36 n � ? ethernet-phy@37 n
� @ ethernet-phy@38 n � A ethernet-phy@39 n � B ethernet-phy@40 n � C ethernet-phy@41 n � D ethernet-phy@42 n � E ethernet-phy@43 n � F ethernet-phy@44 n � G ethernet-phy@45 n � H ethernet-phy@46 n � I ethernet-phy@47 n � J mdio@6110102f8 mscc,ocelot-miim �disabled R \default + n � $ mdio@61101031c mscc,ocelot-miim �ok R \default + n $ ethernet-phy@64 n � O serdes@10808000 microchip,sparx5-serdes � � n �� ] � switch@0x600000000 microchip,sparx5-switch $ n @ @ � � 0cpu dev gcb �xtr fdma � B Iswitch ethernet-ports + port@0 n � � �
� �qsgmii port@1 n � � �
� �qsgmii port@2 n � � �
� �qsgmii port@3 n � � �
� �qsgmii port@4 n � � � � �qsgmii port@5 n � � � � �qsgmii port@6 n � � � � ! �qsgmii port@7 n � � � � " �qsgmii port@8 n � � � � # �qsgmii port@9 n � � � � $ �qsgmii port@10 n
� � � � % �qsgmii port@11 n � � � � & �qsgmii port@12 n � � � � ' �qsgmii port@13 n
� � � � ( �qsgmii port@14 n � � � � ) �qsgmii port@15 n � � � � * �qsgmii port@16 n � � � � + �qsgmii port@17 n � � � � , �qsgmii port@18 n � � � � - �qsgmii port@19 n � � � � . �qsgmii port@20 n � � � � / �qsgmii port@21 n � � � � 0 �qsgmii port@22 n � � � � 1 �qsgmii port@23 n � � � � 2 �qsgmii port@24 n � � � � 3 �qsgmii port@25 n � � � � 4 �qsgmii port@26 n � � � � 5 �qsgmii port@27 n � � � � 6 �qsgmii port@28 n � � � � 7 �qsgmii port@29 n � � � � 8 �qsgmii port@30 n � � � � 9 �qsgmii port@31 n � � � � : �qsgmii port@32 n � � � � ; �qsgmii port@33 n ! � � � � < �qsgmii port@34 n " � � � � = �qsgmii port@35 n # � � � � > �qsgmii port@36 n $ � � � � ? �qsgmii port@37 n % � � � � @ �qsgmii port@38 n & � � � � A �qsgmii port@39 n ' � � � � B �qsgmii port@40 n ( � � � � C �qsgmii port@41 n ) � � � � D �qsgmii port@42 n * � � � � E �qsgmii port@43 n + � � � � F �qsgmii port@44 n , � � � � G �qsgmii port@45 n - � � � � H �qsgmii port@46 n . � � � � I �qsgmii port@47 n / � � � � J �qsgmii port@60 n < � a� �
�10gbase-r � K �in-band-status port@61 n = � a� �
�10gbase-r � L �in-band-status port@62 n > � a� �
�10gbase-r � M �in-band-status port@63 n ? � a� �
�10gbase-r � N �in-band-status port@64 n @ � � � � O �sgmii i2c0-imux@0 i2c-mux-pinctrl + � P ) \i2c_sfp1 i2c_sfp2 i2c_sfp3 i2c_sfp4 idle R Q R S T U i2c_sfp1 n + � V i2c_sfp2 n + � Y i2c_sfp3 n + � Z i2c_sfp4 n + � [ sfp-eth60 sff,sfp * V 2 W C W V X ` X o X � K sfp-eth61 sff,sfp * Y 2 W C W V X ` X o X � L sfp-eth62 sff,sfp * Z 2 W C W V X ` X o X � M sfp-eth63 sff,sfp * [ 2 W C W V X ` X o X � N gpio-restart
gpio-restart V % ~ � leds
gpio-leds led@0
�eth60:yellow V \ �off led@1 �eth60:green V \ �off led@2
�eth61:yellow V \ �off led@3 �eth61:green V \ �off led@4
�eth62:yellow V \ �off led@5 �eth62:green V \ �off led@6
�eth63:yellow V \ �off led@7 �eth63:green V \ �off memory@0 bmemory n compatible interrupt-parent #address-cells #size-cells model spi0 serial0 serial1 stdout-path cpu device_type reg enable-method next-level-cache phandle interrupts interrupt-affinity status #clock-cells clock-frequency clocks ranges #interrupt-cells interrupt-controller #mux-control-cells mux-reg-masks reg-names #reset-cells cpu-syscon pinctrl-0 pinctrl-names reg-io-width reg-shift num-cs spi-max-frequency mux-controls rx-sample-delay-ns clock-names assigned-clocks assigned-clock-rates bus-width gpio-controller #gpio-cells gpio-ranges pins function output-low output-high resets reset-names ngpios microchip,sgpio-port-ranges i2c-sda-hold-time-ns #thermal-sensor-cells #phy-cells interrupt-names microchip,bandwidth phys phy-handle phy-mode sfp managed i2c-parent pinctrl-1 pinctrl-2 pinctrl-3 pinctrl-4 i2c-bus tx-disable-gpios rate-select0-gpios los-gpios mod-def0-gpios tx-fault-gpios priority label default-state