�
�� _� 8 Y� ( % Y` % mediatek,mt7622-rfb1 mediatek,mt7622 + 7MediaTek MT7622 RFB1 board opp-table operating-points-v2 = H opp-300000000 P �À W ~� opp-437500000 P �` W B@ opp-600000000 P #�F W � opp-812500000 P 0m� W �� opp-1025000000 P =B@ W �0 opp-1137500000 P C��` W O� opp-1262500000 P K@8� W � opp-1350000000 P Pw]� W �0 cpus + cpu@0 ecpu arm,cortex-a53 q u |cpu intermediate � � �psci �M|m � � � H cpu@1 ecpu arm,cortex-a53 q u |cpu intermediate � � �psci �M|m � � � H dummy40m fixed-clock �bZ � H oscillator fixed-clock � �}x@ �clkxtal H psci
arm,psci-0.2 �smc pmu arm,cortex-a53-pmu reserved-memory + 0 secmon@43000000 q C 7 thermal-zones cpu-thermal > � T � b
trips cpu-passive r �� ~ � lpassive H cpu-active r � ~ � lactive H cpu-hot r S� ~ � lhot H
cpu-crit r �� ~ � lcritical cooling-maps map0 � � �������� �������� map1 � � �������� �������� map2 �
� �������� �������� timer arm,armv8-timer 0
infracfg@10000000 mediatek,mt7622-infracfg syscon q � � H pwrap@10001000 mediatek,mt7622-pwrap q P �pwrap u |spi wrap � �pwrap � �okay �default � regulators mediatek,mt6380-regulator buck-vcore1 �vcore1 � '�
DV % j : N H buck-vcore �vcore � '�
DV % j : N buck-vrf �vrf � O�
X % : N ldo-vm �vm � �
\� % : N H ldo-va �va � !��
2Z� % : N ldo-vphy �vphy � w@
w@ % : N ldo-vddr �vddr � �
� % : N ldo-vt �vt � !��
2Z� % : N pericfg@10002000 mediatek,mt7622-pericfg syscon q � � H power-controller@10006000 mediatek,mt7622-scpsys syscon ` q ` 0 � � � � t u M |hif_sel H ir-receiver@10009000 mediatek,mt7622-cir q � � u 8 |clk bus �okay �default � interrupt-controller@10200620 . mediatek,mt7622-sysirq mediatek,mt6577-sysirq } � q H efuse@10206000 % mediatek,mt7622-efuse mediatek,efuse q ` + calib@198 q � H clock-controller@10209000 mediatek,mt7622-apmixedsys q � � H clock-controller@10210000 mediatek,mt7622-topckgen q ! � H rng@1020f000 ( mediatek,mt7622-rng mediatek,mt7623-rng q � u |rng pinctrl@10211000 mediatek,mt7622-pinctrl q ! P
�base eint � � � g } � � H emmc-pins-default H % mux �emmc �emmc emmc_rst conf-cmd-dat , �NDL0 NDL1 NDL2 NDL3 NDL4 NDL5 NDL6 NDL7 NRB � � conf-clk �NCLE � emmc-pins-uhs H & mux �emmc �emmc conf-cmd-dat , �NDL0 NDL1 NDL2 NDL3 NDL4 NDL5 NDL6 NDL7 NRB � � conf-clk �NCLE � eth-pins H < mux �eth �mdc_mdio rgmii_via_gmac2 i2c1-pins H mux �i2c �i2c1_0 i2c2-pins H mux �i2c �i2c2_0 i2s1-pins mux �i2s 0 �i2s_out_mclk_bclk_ws i2s1_in_data i2s1_out_data conf * �I2S1_IN I2S1_OUT I2S_BCLK I2S_WS I2S_MCLK � irrx-pins H mux �ir �ir_1_rx irtx-pins mux �ir �ir_1_tx parallel-nand-pins H ! mux �flash �par_nand pcie0-pins H 2 mux �pcie - �pcie0_pad_perst pcie0_1_waken pcie0_1_clkreq pcie1-pins mux �pcie - �pcie1_pad_perst pcie1_0_waken pcie1_0_clkreq pmic-bus-pins H mux �pmic �pmic_bus pwm1-2-pins H mux �pwm
�pwm_ch7_2 wled-pins mux �led �wled sd0-pins-default H ) mux �sd �sd_0 conf-cmd-data * �I2S2_OUT I2S4_IN I2S3_IN I2S2_IN I2S4_OUT � � conf-clk �I2S3_OUT � conf-cd �TXD3 � sd0-pins-uhs H * mux �sd �sd_0 conf-cmd-data * �I2S2_OUT I2S4_IN I2S3_IN I2S2_IN I2S4_OUT � � conf-clk �I2S3_OUT � serial-nand-pins mux �flash �snfi spic0-pins H mux �spi �spic0_0 spic1-pins H # mux �spi �spic1_0 spi-nor-pins H " mux �flash �spi_nor uart0-pins H mux �uart �uart0_0_tx_rx uart2-pins H mux �uart �uart2_1_tx_rx watchdog-pins H mux �watchdog �watchdog wmac-pins H + mux �antsel � �antsel0 antsel1 antsel2 antsel3 antsel4 antsel5 antsel6 antsel7 antsel8 antsel9 antsel12 antsel13 antsel14 antsel15 antsel16 antsel17 watchdog@10212000 ( mediatek,mt7622-wdt mediatek,mt6589-wdt q ! �default � �okay rtc@10212800 % mediatek,mt7622-rtc mediatek,soc-rtc q !( � u |rtc interrupt-controller@10300000 arm,gic-400 } � @ q 1 2 4 6 H cci@10390000 arm,cci-400 + q 9 0 9 slave-if@1000 arm,cci-400-ctrl-if ace-lite q slave-if@4000 arm,cci-400-ctrl-if ace q @ slave-if@5000 arm,cci-400-ctrl-if syscon ace q P H pmu@9000 arm,cci-400-pmu,r1 q � P < : ; < = > adc@11001000 mediatek,mt7622-auxadc q u |main ' H serial@11002000 * mediatek,mt7622-uart mediatek,mt6577-uart q [ u @
|baud bus �okay �default � serial@11003000 * mediatek,mt7622-uart mediatek,mt6577-uart q 0 \ u @ |baud bus �disabled serial@11004000 * mediatek,mt7622-uart mediatek,mt6577-uart q @ ] u @ |baud bus �okay �default � serial@11005000 * mediatek,mt7622-uart mediatek,mt6577-uart q P ^ u @ |baud bus �disabled pwm@11006000 mediatek,mt7622-pwm q ` 9 M @ u < ' |top main pwm1 pwm2 pwm3 pwm4 pwm5 pwm6 �okay �default � i2c@11007000 mediatek,mt7622-i2c q p � � T D u
|main dma + �disabled i2c@11008000 mediatek,mt7622-i2c q � � � � U D u
|main dma + �okay �default � i2c@11009000 mediatek,mt7622-i2c q � � � V D u
|main dma + �okay �default � spi@1100a000 mediatek,mt7622-spi q � v u A |parent-clk sel-clk spi-clk + �okay �default � thermal@1100b000 N mediatek,mt7622-thermal q � N u
|therm auxadc � d t � �calibration-data H
serial@1100c000 ' mediatek,mt7622-btif mediatek,mtk-btif q � Z u |main � � �okay bluetooth mediatek,mt7622-bluetooth � u |ref nfi@1100d000 mediatek,mt7622-nfc q � ` u |nfi_clk pad_clk � + �disabled �default � ! ecc@1100e000 mediatek,mt7622-ecc q � _ u |nfiecc_clk �disabled H spi@11014000 ( mediatek,mt7622-nor mediatek,mt8173-nor q @ � u ? |spi sf + �disabled �default � " flash@0 jedec,spi-nor q spi@11016000 mediatek,mt7622-spi q ` z u B |parent-clk sel-clk spi-clk + �okay �default � # serial@11019000 * mediatek,mt7622-uart mediatek,mt6577-uart q � Y u @ |baud bus �disabled clock-controller@11220000 mediatek,mt7622-audsys syscon q " � H $ audio-controller mediatek,mt7622-audio � � �afe asys u P Q k l Y Z [ \ _ ` a b g h i j $ $ $
$ $ $ $ $ $ $ $ ' $ ( $ $ . $ $ � |infra_sys_audio_clk top_audio_mux1_sel top_audio_mux2_sel top_audio_a1sys_hp top_audio_a2sys_hp i2s0_src_sel i2s1_src_sel i2s2_src_sel i2s3_src_sel i2s0_src_div i2s1_src_div i2s2_src_div i2s3_src_div i2s0_mclk_en i2s1_mclk_en i2s2_mclk_en i2s3_mclk_en i2so0_hop_ck i2so1_hop_ck i2so2_hop_ck i2so3_hop_ck i2si0_hop_ck i2si1_hop_ck i2si2_hop_ck i2si3_hop_ck asrc0_out_ck asrc1_out_ck asrc2_out_ck asrc3_out_ck audio_afe_pd audio_afe_conn_pd audio_a1sys_pd audio_a2sys_pd � F G c d � 1 2 � � mmc@11230000 mediatek,mt7622-mmc q # O u C |source hclk � �hrst �okay �default state_uhs � % ! & + 5�� C U d ' p ( � D � . } mmc@11240000 mediatek,mt7622-mmc q $ P u 8 |source hclk � �hrst �okay �default state_uhs � ) ! * + 5�� � � � Q d ' p ' � E � . wmac@18000000 mediatek,mt7622-wmac q � � �okay � �default � + clock-controller@1a000000 mediatek,mt7622-ssusbsys q � � H , usb@1a0c0000 ' mediatek,mt7622-xhci mediatek,mtk-xhci q G �mac ippc � � u , , , , |sys_ck ref_ck mcu_ck dma_ck � - . / �okay � ' � 0 t-phy@1a0c4000 . mediatek,mt7622-tphy mediatek,generic-tphy-v1 q @ + 0 �okay usb-phy@1a0c4800 q H � u , |ref H - usb-phy@1a0c4900 q I � u |ref H . usb-phy@1a0c5000 q P � u , |ref H / clock-controller@1a100800 mediatek,mt7622-pciesys q � � H 1 pcie@1a140000 mediatek,mt7622-pcie epci 0 q 0 P �subsys port0 port1 + � � ` u 1
1 1 1 1 1 1 1 1 1 1 1 d |sys_ck0 sys_ck1 ahb_ck0 ahb_ck1 aux_ck0 aux_ck1 axi_ck0 axi_ck1 obff_ck0 obff_ck1 pipe_ck0 pipe_ck1 � � � 0� �okay �default � 2 pcie@0,0 q + � 0 �okay � ` 3 3 3 3 interrupt-controller } � H 3 pcie@1,0 q + � 0 �disabled � ` 4 4 4 4 interrupt-controller } � H 4 sata@1a200000 ' mediatek,mt7622-ahci mediatek,mtk-ahci q � �hostc ( u 1 1
1 1 1 |ahb axi asic rbc pm � 5 sata-phy � � 1 1
1 �axi sw reg / 1 �okay t-phy@1a243000 . mediatek,mt7622-tphy mediatek,generic-tphy-v1 + 0 �okay sata-phy@1a243000 q $0 u 7 |ref � H 5 clock-controller@1af00000 mediatek,mt7622-hifsys q � p � H ; clock-controller@1b000000 mediatek,mt7622-ethsys syscon q � � H 6 dma-controller@1b007000 mediatek,mt7622-hsdma q p � u 6 |hsdma � A pcie-mirror@10000400 # mediatek,mt7622-pcie-mirror syscon q H : wed@1020a000 mediatek,mt7622-wed syscon q � � H 8 wed@1020b000 mediatek,mt7622-wed syscon q � � H 9 ethernet@1b100000 mediatek,mt7622-eth q $ � � � X u ; 6 6 6 6 7 7 7 7 / \ |ethif esw gp0 gp1 gp2 sgmii_tx250m sgmii_rx250m sgmii_cdr_ref sgmii_cdr_fb sgmii_ck eth2pll � L 6 \ 7 n � 8 9 � : � ; � + �okay �default � < mac@0 mediatek,eth-mac q 82500base-x H = fixed-link O � � � mdio-bus + switch@0 mediatek,mt7531 q � 6 ports + port@0 q �lan0 port@1 q �lan1 port@2 q �lan2 port@3 q �lan3 port@4 q �wan port@6 q �cpu � = 82500base-x fixed-link O � � � sgmiisys@1b128000 mediatek,mt7622-sgmiisys syscon q � 0 � H 7 aliases �/serial@11002000 chosen �serial0:115200n8 0 earlycon=uart8250,mmio32,0x11002000 swiotlb=512 gpio-keys
gpio-keys d factory �factory � wps �wps � f memory@40000000 q @ ememory regulator-1p8v regulator-fixed �fixed-1.8V � w@
w@ : H ( regulator-3p3v regulator-fixed �fixed-3.3V � 2Z�
2Z� N : H ' regulator-5v regulator-fixed �fixed-5V � LK@
LK@ N : H 0 compatible interrupt-parent #address-cells #size-cells model opp-shared phandle opp-hz opp-microvolt device_type reg clocks clock-names operating-points-v2 #cooling-cells enable-method clock-frequency cci-control-port proc-supply sram-supply #clock-cells clock-output-names interrupts interrupt-affinity ranges no-map polling-delay-passive polling-delay thermal-sensors temperature hysteresis trip cooling-device #reset-cells reg-names resets reset-names status pinctrl-names pinctrl-0 regulator-name regulator-min-microvolt regulator-max-microvolt regulator-ramp-delay regulator-always-on regulator-boot-on #power-domain-cells infracfg interrupt-controller #interrupt-cells gpio-controller #gpio-cells gpio-ranges function groups pins input-enable bias-pull-up bias-pull-down drive-strength interface-type #io-channel-cells #pwm-cells clock-div #thermal-sensor-cells mediatek,auxadc mediatek,apmixedsys nvmem-cells nvmem-cell-names reg-shift reg-io-width power-domains ecc-engine interrupt-names assigned-clocks assigned-clock-parents assigned-clock-rates pinctrl-1 bus-width max-frequency cap-mmc-highspeed mmc-hs200-1_8v vmmc-supply vqmmc-supply non-removable cap-sd-highspeed r_smpl cd-gpios mediatek,infracfg phys vusb33-supply vbus-supply #phy-cells bus-range interrupt-map-mask interrupt-map phy-names ports-implemented mediatek,phy-mode #dma-cells mediatek,ethsys mediatek,sgmiisys mediatek,cci-control mediatek,wed mediatek,pcie-mirror mediatek,hifsys dma-coherent full-duplex pause reset-gpios label ethernet serial0 stdout-path bootargs poll-interval linux,code