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�� � 8 z� ( ` zx $ mediatek,mt8173-evb mediatek,mt8173 + ! 7MediaTek MT8173 evaluation board aliases =/soc/ovl@1400c000 B/soc/ovl@1400d000 G/soc/rdma@1400e000 M/soc/rdma@1400f000 S/soc/rdma@14010000 Y/soc/wdma@14011000 _/soc/wdma@14012000 e/soc/color@14013000 l/soc/color@14014000 s/soc/split@14018000 z/soc/split@14019000 �/soc/dpi@1401d000 �/soc/dsi@1401b000 �/soc/dsi@1401c000 �/soc/rdma@14001000 �/soc/rdma@14002000 �/soc/rsz@14003000 �/soc/rsz@14004000 �/soc/rsz@14005000 �/soc/wdma@14006000 �/soc/wrot@14007000 �/soc/wrot@14008000 �/soc/serial@11002000 �/soc/serial@11003000 �/soc/serial@11004000 �/soc/serial@11005000 opp_table0 operating-points-v2 � opp-507000000 84�
x opp-702000000 )�
�� opp-1001000000 ;� @ �� opp-1105000000 A�@ eh opp-1209000000 H�@ � opp-1300000000 M|m � opp-1508000000 Y�A � opp-1703000000 e��� *� opp_table1 operating-points-v2 � opp-507000000 84� �` opp-702000000 )�
:� opp-1001000000 ;� @ % opp-1209000000 H�@ �@ opp-1404000000 S�W ]� opp-1612000000 `+ � opp-1807000000 k��� �� opp-2106000000 }�� *� cpus + cpu-map cluster0 core0 % core1 % cluster1 core0 % core1 % cpu@0 )cpu arm,cortex-a53 5 9psci G W f �
�cpu intermediate � � � �
cpu@1 )cpu arm,cortex-a53 5 9psci G W f �
�cpu intermediate � � � �
cpu@100 )cpu arm,cortex-a72 5 9psci G W f � �cpu intermediate � � � �
cpu@101 )cpu arm,cortex-a72 5 9psci G W f � �cpu intermediate � � � �
idle-states �psci cpu-sleep-0 arm,idle-state � � � @ " pmu_a53 arm,cortex-a53-pmu 9 D pmu_a72 arm,cortex-a72-pmu 9
D psci # arm,psci-1.0 arm,psci-0.2 arm,psci @smc W� c� k� oscillator0 fixed-clock r ��� �clk26m oscillator1 fixed-clock r } �clk32k oscillator2 fixed-clock r �cpum_ck thermal-zones cpu-thermal � � � � � � � trips trip-point0 � � � � 0passive trip-point1 � L � � 0passive cpu_crit0 � �8 � � 0critical cooling-maps map0 � �������� �������� map1 � �������� �������� reserved-memory + vpu_dma_mem_region@b7000000 shared-dma-pool 5 � P ' 1 timer arm,armv8-timer 0 9
8 soc + simple-bus clock-controller@10000000 mediatek,mt8173-topckgen 5 r power-controller@10001000 mediatek,mt8173-infracfg syscon 5 r O power-controller@10003000 mediatek,mt8173-pericfg syscon 5 0 r O syscfg_pctl_a@10005000 % mediatek,mt8173-pctl-a-syscfg syscon 5 P pinctrl@1000b000 mediatek,mt8173-pinctrl 5 � \ q � � � � $ 9 � � � xxx A pins1 � � � i2c0 pins1 � - . � i2c1 pins1 � } ~ � i2c2 ! pins1 � + , � i2c3 % pins1 � j k � i2c4 & pins1 � � � � i2c6 ' pins1 � d e � disp_pwm0_pins ? pins1 � W � mmc0default ( pins_cmd_dat $ � 9 : ; < = > ? @ B � pins_clk � A � pins_rst � D mmc1default , pins_cmd_dat � I J K L N �
f pins_clk � M �
pins_insert � � mmc0 ) pins_cmd_dat $ � 9 : ; < = > ? @ B �
e pins_clk � A
� e pins_rst � D mmc1 - pins_cmd_dat � I J K L N �
f pins_clk � M
� f usb_iddig_pull_up 6 pins_iddig � usb_iddig_pull_down pins_iddig � � spi0 " pins_spi � E F G H syscon@10006000 syscon simple-mfd 5 ` power-controller ! mediatek,mt8173-power-controller + power-domain@0 5 � U �mm power-domain@1 5 � U X �mm venc power-domain@2 5 � U �mm power-domain@3 5 � U �mm 0 power-domain@4 5 � U i
�mm venclt power-domain@5 5 power-domain@6 5 power-domain@7 5 � �mfg + B power-domain@8 5 + power-domain@9 5 0 watchdog@10007000 ( mediatek,mt8173-wdt mediatek,mt6589-wdt 5 p timer@10008000 , mediatek,mt8173-timer mediatek,mt6577-timer 5 � 9 � � x pwrap@1000d000 mediatek,mt8173-pwrap 5 � Ppwrap 9 � Z apwrap �
�spi wrap m mt6397 mediatek,mt6397 9 � � regulators mediatek,mt6397-regulator buck_vpca15 {vpca15 �
�` � �p � 0� �
buck_vpca7 {vpca7 �
�` � �p � 0� � s buck_vsramca15
{vsramca15 �
�` � �p � 0� � buck_vsramca7 {vsramca7 �
�` � �p � 0� �
buck_vcore {vcore �
�` � �p � 0� � buck_vgpu {vgpu �
�` � �p � 0� � s buck_vdrm {vdrm � O� � \� � 0� � buck_vio18 {vio18 � � � 6` � 0� � + ldo_vtcxo {vtcxo � ldo_va28 {va28 � ldo_vcama {vcama � �` � *�� � � ldo_vio28 {vio28 � ldo_vusb {vusb 3 ldo_vmc {vmc � w@ � 2Z� � � / ldo_vmch {vmch � -� � 2Z� � � . ldo_vemc3v3 {vemc_3v3 � -� � 2Z� � � * ldo_vgp1 {vcamd � �� � 2Z� � � ldo_vgp2 {vcamio � B@ � 2Z� � � ldo_vgp3 {vcamaf � O� � 2Z� � � ldo_vgp4 {vgp4 � O� � 2Z� � � ldo_vgp5 {vgp5 � O� � -� � � ldo_vgp6 {vgp6 � O� � 2Z� � � ldo_vibr {vibr � � � 2Z� � � cec@10013000 mediatek,mt8173-cec 5 0 � 9 � � �okay vpu@10020000 mediatek,mt8173-vpu 5 Ptcm cfg_reg 9 � � g �main ; intpol-controller@10200620 . mediatek,mt8173-sysirq mediatek,mt6577-sysirq � � 5 iommu@10205000 mediatek,mt8173-m4u 5 P 9 � � �bclk # : efuse@10206000 mediatek,mt8173-efuse 5 ` + calib@528 5 ( $ clock-controller@10209000 mediatek,mt8173-apmixedsys 5 � r hdmi-phy@10209100 mediatek,mt8173-hdmi-phy 5 � $ � �pll_ref �hdmitx_dig_cts 0
? r Q �okay B mailbox@10212000 mediatek,mt8173-gce 5 ! 9 � � �gce \ 8 dsi-phy@10215000 mediatek,mt8173-mipi-tx 5 !P �
�mipi_tx0_pll r Q �disabled < dsi-phy@10216000 mediatek,mt8173-mipi-tx 5 !` �
�mipi_tx1_pll r Q �disabled = interrupt-controller@10221000 arm,gic-400 � � @ 5 " " "@ "` 9 auxadc@11001000 mediatek,mt8173-auxadc 5 � �main h # serial@11002000 * mediatek,mt8173-uart mediatek,mt6577-uart 5 9 S � $ �baud bus �okay serial@11003000 * mediatek,mt8173-uart mediatek,mt6577-uart 5 0 9 T � % �baud bus �disabled serial@11004000 * mediatek,mt8173-uart mediatek,mt6577-uart 5 @ 9 U � & �baud bus �disabled serial@11005000 * mediatek,mt8173-uart mediatek,mt6577-uart 5 P 9 V � ' �baud bus �disabled i2c@11007000 mediatek,mt8173-i2c 5 p p � 9 L z �
�main dma �default � + �disabled i2c@11008000 mediatek,mt8173-i2c 5 � p � � 9 M z �
�main dma �default � + �okay da9211@68 dlg,da9211 5 h regulators BUCKA {VBUCKA �
�` � �0 � �� � C#� � ' � BUCKB {VBUCKB �
�` � �0 � �� � -� � ' i2c@11009000 mediatek,mt8173-i2c 5 � p � 9 N z �
�main dma �default � ! + �disabled spi@1100a000 mediatek,mt8173-spi + 5 � 9 n � 4 \ �parent-clk sel-clk spi-clk �okay �default � " � thermal@1100b000 � mediatek,mt8173-thermal 5 � 9 F �
�therm auxadc Z � # $ $calibration-data spi@1100d000 mediatek,mt8173-nor 5 � � � ! r �spi sf + �disabled i2c@11010000 mediatek,mt8173-i2c 5 p � � 9 O z �
�main dma �default � % + �disabled i2c@11011000 mediatek,mt8173-i2c 5 p � 9 P z �
�main dma �default � & + �disabled i2c@11012000 mediatek,mt8173-hdmi-ddc 9 Q 5 � �ddc-i2c i2c@11013000 mediatek,mt8173-i2c 5 0 p � � 9 R z � #
�main dma �default � ' + �disabled audio-controller@11220000 mediatek,mt8173-afe-pcm 5 " 9 � m P � d e y � � � � � b �infra_sys_audio_clk top_pdn_audio top_pdn_aud_intbus bck0 bck1 i2s0_m i2s1_m i2s2_m i2s3_m i2s3_b 5 m n E mmc@11230000 mediatek,mt8173-mmc 5 # 9 G � _ �source hclk �okay �default state_uhs � ( \ ) f p�� ~ � � � � * � + mmc@11240000 mediatek,mt8173-mmc 5 $ 9 H � R �source hclk �okay �default state_uhs � , \ - f p�� % 2 � � . � / mmc@11250000 mediatek,mt8173-mmc 5 % 9 I � R �source hclk �disabled mmc@11260000 mediatek,mt8173-mmc 5 & 9 J � u �source hclk �disabled usb@11271000 # mediatek,mt8173-mtu3 mediatek,mtu3 5 ' 0 ( Pmac ippc 9 @ ; 0 1 2 m � ^ �sys_ck ref_ck @ + �okay W 3 e 4 q 5 xotg � �default � 6 usb@11270000 ' mediatek,mt8173-xhci mediatek,mtk-xhci 5 ' Pmac 9 s m � ^ �sys_ck ref_ck �okay W 3 e 7 t-phy@11290000 mediatek,mt8173-u3phy 5 ) + �okay usb-phy@11290800 5 ) � �ref Q �okay 0 usb-phy@11290900 5 ) � �ref Q �okay 1 usb-phy@11291000 5 ) � �ref Q �okay 2 syscon@14000000 mediatek,mt8173-mmsys syscon 5 m 5 U �ׄ r � 8 8 � 8 9 rdma@14001000 - mediatek,mt8173-mdp-rdma mediatek,mt8173-mdp 5 � 9 9 m � : � � ; rdma@14002000 mediatek,mt8173-mdp-rdma 5 � 9 9 m � : � � rsz@14003000 mediatek,mt8173-mdp-rsz 5 0 � 9 m rsz@14004000 mediatek,mt8173-mdp-rsz 5 @ � 9 m rsz@14005000 mediatek,mt8173-mdp-rsz 5 P � 9 m wdma@14006000 mediatek,mt8173-mdp-wdma 5 ` � 9 m � : � wrot@14007000 mediatek,mt8173-mdp-wrot 5 p � 9 m � : � wrot@14008000 mediatek,mt8173-mdp-wrot 5 � � 9
m � : � � ovl@1400c000 mediatek,mt8173-disp-ovl 5 � 9 � m � 9 � : � � 8 � ovl@1400d000 mediatek,mt8173-disp-ovl 5 � 9 � m � 9 � : � � � 8 � rdma@1400e000 mediatek,mt8173-disp-rdma 5 � 9 � m � 9 � : � � 8 � rdma@1400f000 mediatek,mt8173-disp-rdma 5 � 9 � m � 9 � : � � � 8 � rdma@14010000 mediatek,mt8173-disp-rdma 5 9 � m � 9 � : � � � 8 wdma@14011000 mediatek,mt8173-disp-wdma 5 9 � m � 9 � : � � 8 wdma@14012000 mediatek,mt8173-disp-wdma 5 9 � m � 9 � : � � � 8 color@14013000 mediatek,mt8173-disp-color 5 0 9 � m � 9 � 8 0 color@14014000 mediatek,mt8173-disp-color 5 @ 9 � m � 9 � 8 @ aal@14015000 mediatek,mt8173-disp-aal 5 P 9 � m � 9 � 8 P gamma@14016000 mediatek,mt8173-disp-gamma 5 ` 9 � m � 9 � 8 ` merge@14017000 mediatek,mt8173-disp-merge 5 p m � 9 split@14018000 mediatek,mt8173-disp-split 5 � m � 9 split@14019000 mediatek,mt8173-disp-split 5 � m � 9 ufoe@1401a000 mediatek,mt8173-disp-ufoe 5 � 9 � m � 9 dsi@1401b000 mediatek,mt8173-dsi 5 � 9 � m � 9 $ 9 % < �engine digital hs ; < �dphy �disabled dsi@1401c000 mediatek,mt8173-dsi 5 � 9 � m � 9 & 9 ' = �engine digital hs ; = �dphy �disabled dpi@1401d000 mediatek,mt8173-dpi 5 � 9 � m � 9 ( 9 ) �pixel engine pll �okay port endpoint � > C pwm@1401e000 mediatek,mt8173-disp-pwm 5 � � � 9 ! 9 �main mm �okay �default � ? pwm@1401f000 mediatek,mt8173-disp-pwm 5 � � � 9 # 9 " �main mm �disabled mutex@14020000 mediatek,mt8173-disp-mutex 5 9 � m � 9 5 6 larb@14021000 mediatek,mt8173-smi-larb 5 @ m � 9 9 �apb smi smi@14022000 mediatek,mt8173-smi-common 5 m � 9 9 �apb smi @ od@14023000 mediatek,mt8173-disp-od 5 0 � 9 hdmi@14025000 mediatek,mt8173-hdmi 5 P 9 � � 9 , 9 - 9 . 9 / �pixel pll bclk spdif �default � A ; B �hdmi * 9 5 s E B �okay ports + port@0 5 endpoint � C > port@1 5 endpoint � D I larb@14027000 mediatek,mt8173-smi-larb 5 p @ m � 9 2 9 2 �apb smi clock-controller@15000000 mediatek,mt8173-imgsys syscon 5 r E larb@15001000 mediatek,mt8173-smi-larb 5 @ m � E E �apb smi clock-controller@16000000 mediatek,mt8173-vdecsys syscon 5 r F vcodec@16000000 mediatek,mt8173-vcodec-dec � 5 0 @ P h p x � 9 � � @ � : : ! : % : & : ' : " : # : $ � ; m @ �
> l W M i N Z �vcodecpll univpll_d2 clk_cci400_sel vdec_sel vdecpll vencpll venc_lt_sel vdec_bus_clk_src ( 5 i l W
E N > M � XU��/� larb@16010000 mediatek,mt8173-smi-larb 5 @ m � F F �apb smi clock-controller@18000000 mediatek,mt8173-vencsys syscon 5 r G larb@18001000 mediatek,mt8173-smi-larb 5 @ m � G G �apb smi vcodec@18002000 mediatek,mt8173-vcodec-enc 5 9 � � X � : ` : a : b : c : d : i : j : k : l : m : n � ; � X �venc_sel 5 X E M jpegdec@18004000 mediatek,mt8173-jpgdec 5 @ 9 � � G G �jpgdec-smi jpgdec m � � : g : h clock-controller@19000000 ! mediatek,mt8173-vencltsys syscon 5 r H larb@19001000 mediatek,mt8173-smi-larb 5 @ m � H H �apb smi vcodec@19002000 mediatek,mt8173-vcodec-enc-vp8 5 9 � H � : � : � : � : � : � : � : � : � : � � � ; � i �venc_lt_sel 5 i E N memory@40000000 )memory 5 @ � chosen connector hdmi-connector ?hdmi 0d port endpoint � I D extcon_iddig linux,extcon-usb-gpio E 5 regulator-usb-p1 regulator-fixed {usb_vbus � LK@ � LK@ H � M 7 regulator-usb-p0 regulator-fixed {vbus � LK@ � LK@ H M 4 compatible interrupt-parent #address-cells #size-cells model ovl0 ovl1 rdma0 rdma1 rdma2 wdma0 wdma1 color0 color1 split0 split1 dpi0 dsi0 dsi1 mdp-rdma0 mdp-rdma1 mdp-rsz0 mdp-rsz1 mdp-rsz2 mdp-wdma0 mdp-wrot0 mdp-wrot1 serial0 serial1 serial2 serial3 opp-shared phandle opp-hz opp-microvolt cpu device_type reg enable-method cpu-idle-states #cooling-cells dynamic-power-coefficient clocks clock-names operating-points-v2 capacity-dmips-mhz proc-supply sram-supply entry-method local-timer-stop entry-latency-us exit-latency-us min-residency-us arm,psci-suspend-param interrupts interrupt-affinity cpu_suspend cpu_off cpu_on #clock-cells clock-frequency clock-output-names polling-delay-passive polling-delay thermal-sensors sustainable-power temperature hysteresis trip cooling-device contribution ranges alignment no-map arm,no-tick-in-suspend #reset-cells mediatek,pctl-regmap pins-are-numbered gpio-controller #gpio-cells interrupt-controller #interrupt-cells pinmux input-enable bias-pull-down bias-disable output-low bias-pull-up drive-strength #power-domain-cells mediatek,infracfg domain-supply reg-names resets reset-names power-domains regulator-name regulator-min-microvolt regulator-max-microvolt regulator-ramp-delay regulator-always-on regulator-enable-ramp-delay status memory-region mediatek,larbs #iommu-cells mediatek,ibias mediatek,ibias_up #phy-cells #mbox-cells #io-channel-cells clock-div pinctrl-names pinctrl-0 regulator-min-microamp regulator-max-microamp mediatek,pad-select #thermal-sensor-cells mediatek,auxadc mediatek,apmixedsys nvmem-cells nvmem-cell-names assigned-clocks assigned-clock-parents pinctrl-1 bus-width max-frequency cap-mmc-highspeed mediatek,hs200-cmd-int-delay mediatek,hs400-cmd-int-delay mediatek,hs400-cmd-resp-sel-rising vmmc-supply vqmmc-supply non-removable cap-sd-highspeed sd-uhs-sdr25 cd-gpios phys mediatek,syscon-wakeup vusb33-supply vbus-supply extcon dr_mode wakeup-source assigned-clock-rates mboxes mediatek,gce-client-reg iommus mediatek,larb mediatek,vpu phy-names remote-endpoint #pwm-cells mediatek,gce-events mediatek,smi mediatek,syscon-hdmi label id-gpio enable-active-high