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�� )� 8 'l ( " '4 $ mediatek,mt8192-evb mediatek,mt8192 + ! 7MediaTek MT8192 evaluation board oscillator0 fixed-clock = J��� Zclk26m m oscillator1 fixed-clock = J � Zclk32k cpus + cpu@0 ucpu arm,cortex-a55 � �psci Jec3@ � � � � � m cpu@100 ucpu arm,cortex-a55 � �psci Jec3@ � � � � � m
cpu@200 ucpu arm,cortex-a55 � �psci Jec3@ � � � � � m cpu@300 ucpu arm,cortex-a55 � �psci Jec3@ � � � � � m cpu@400 ucpu arm,cortex-a76 � �psci J�f� � � � � m
cpu@500 ucpu arm,cortex-a76 � �psci J�f� � � � � m cpu@600 ucpu arm,cortex-a76 � �psci J�f� � � � � m cpu@700 ucpu arm,cortex-a76 � �psci J�f� � � � � m cpu-map cluster0 core0 � core1 �
core2 � core3 � core4 �
core5 � core6 � core7 � l2-cache0 cache � m l2-cache1 cache � m l3-cache cache m idle-states �psci cpu-sleep-l arm,idle-state � 7 % � 5 m cpu-sleep-b arm,idle-state � # % � 5 � m cluster-sleep-l arm,idle-state � < % � 5 \ m cluster-sleep-b arm,idle-state � ( % � 5 m pmu-a55 arm,cortex-a55-pmu F pmu-a76 arm,cortex-a76-pmu F psci
arm,psci-1.0 �smc timer arm,armv8-timer @ F
J �]@ soc + simple-bus Q performance-controller@11bc10 mediatek,cpufreq-hw � � �0 X m interrupt-controller@c000000 arm,gic-v3 r � � � F m ppi-partitions interrupt-partition-0 �
m interrupt-partition-1 �
m pinctrl@10005000 mediatek,mt8192-pinctrl � � P � � � � � � � � � � ] �iocfg0 iocfg_rm iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_lb iocfg_rt iocfg_lt iocfg_tl eint � � � � � F � r m timer@10017000 , mediatek,mt8192-timer mediatek,mt6765-timer � p F � � �clk13m serial@11002000 * mediatek,mt8192-uart mediatek,mt6577-uart � F m � �baud bus �okay serial@11003000 * mediatek,mt8192-uart mediatek,mt6577-uart � 0 F n � �baud bus �disabled spi@1100a000 ( mediatek,mt8192-spi mediatek,mt6765-spi + � � F � � �parent-clk sel-clk spi-clk �disabled spi@11010000 ( mediatek,mt8192-spi mediatek,mt6765-spi + � F � � �parent-clk sel-clk spi-clk �disabled spi@11012000 ( mediatek,mt8192-spi mediatek,mt6765-spi + � F � � �parent-clk sel-clk spi-clk �disabled spi@11013000 ( mediatek,mt8192-spi mediatek,mt6765-spi + � 0 F � � �parent-clk sel-clk spi-clk �disabled spi@11018000 ( mediatek,mt8192-spi mediatek,mt6765-spi + � � F � � �parent-clk sel-clk spi-clk �disabled spi@11019000 ( mediatek,mt8192-spi mediatek,mt6765-spi + � � F � � �parent-clk sel-clk spi-clk �disabled spi@1101d000 ( mediatek,mt8192-spi mediatek,mt6765-spi + � � F � � �parent-clk sel-clk spi-clk �disabled spi@1101e000 ( mediatek,mt8192-spi mediatek,mt6765-spi + � � F � � �parent-clk sel-clk spi-clk �disabled spi@11234000 mediatek,mt8192-nor � #@ � F � � �spi sf axi + �disabled i2c3@11cb0000 mediatek,mt8192-i2c � � !s � F s � �main dma + �disabled i2c7@11d00000 mediatek,mt8192-i2c � � !v � F w � �main dma + �disabled i2c8@11d01000 mediatek,mt8192-i2c � � !w� � F x � �main dma + �disabled i2c9@11d02000 mediatek,mt8192-i2c � � !y � F y � �main dma + �disabled i2c1@11d20000 mediatek,mt8192-i2c � � !q � F q � �main dma + �disabled i2c2@11d21000 mediatek,mt8192-i2c � � !q� � F r � �main dma + �disabled i2c4@11d22000 mediatek,mt8192-i2c � � !s� � F t � �main dma + �disabled i2c5@11e00000 mediatek,mt8192-i2c � � !u � F u � �main dma + �disabled i2c0@11f00000 mediatek,mt8192-i2c � � !p� � F p � �main dma + �disabled i2c6@11f01000 mediatek,mt8192-i2c � � !u� � F v � �main dma + �disabled aliases /soc/serial@11002000 chosen serial0:921600n8 memory@40000000 umemory � @ � compatible interrupt-parent #address-cells #size-cells model #clock-cells clock-frequency clock-output-names phandle device_type reg enable-method cpu-idle-states next-level-cache performance-domains capacity-dmips-mhz cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us interrupts ranges #performance-domain-cells #interrupt-cells #redistributor-regions interrupt-controller affinity reg-names gpio-controller #gpio-cells gpio-ranges clocks clock-names status clock-div serial0 stdout-path